參數(shù)資料
型號(hào)： ADSP-2186MKST-300
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： DSP Microcomputer
中文描述： 24-BIT, 37.5 MHz, OTHER DSP, PQFP100
封裝： METRIC, PLASTIC, TQFP-100
文件頁(yè)數(shù)： 13/40頁(yè)
文件大?。?/td> 288K
代理商： ADSP-2186MKST-300
REV. 0
ADSP-2186M
–13–
Data Memory
Data Memory (Full Memory Mode)
is a 16-bit-wide space used
for the storage of data variables and for memory-mapped control
registers. The ADSP-2186M has 8K words on Data Memory
RAM on-chip. Part of this space is used by 32 memory-mapped
registers. Support also exists for up to two 8K external memory
overlay spaces through the external data bus. All internal accesses
ACCESSIBLE WHEN
DMOVLAY = 2
ACCESSIBLE WHEN
DMOVLAY = 1
0
x
0000
–
0
x
1FFF
1
0
x
0000
–
0
x
1FFF
1
EXTERNAL
MEMORY
32 MEMORY
MAPPED
REGISTERS
0
x
3FFF
INTERNAL
8160 WORDS
0
x
0000
DATA MEMORY
ADDR
0
x
3FE0
0
x
3FDF
EXTERNAL 8K
DMOVLAY = 1, 2
0
x
1FFF
0
x
2000
DM OVLAY = 0
RESERVED
0
x
0000
–
0
x
1FFF
DATA MEMORY
ALWAYS
ACCESSIBLE
AT ADDRESS
0
x
2000
–
0
x
3FFF
NOTE:
1
SEE TABLE IV FOR DMOVLAY BITS
Figure 5. Data Memory Map
complete in one cycle. Accesses to external memory are timed
using the wait states specified by the DWAIT register and the
wait state mode bit.
Data Memory (Host Mode)
allows access to all internal
memory. External overlay access is limited by a single external
address line (A0).
Table IV. DMOVLAY Bits
DMOVLAY
Memory
A13
A12:0
0
1
2
Reserved
External Overlay 1
External Overlay 2
Not Applicable
0
1
Not Applicable
13 LSBs of Address Between 0x2000 and 0x3FFF
13 LSBs of Address Between 0x2000 and 0x3FFF
Memory Mapped Registers (New to the ADSP-2186M)
The ADSP-2186M has three memory mapped registers that differ
from other ADSP-21xx Family DSPs. The slight modifications
to these registers (Wait State Control, Programmable Flag and
Composite Select Control, and System Control) provide the
ADSP-2186M’s wait state and
BMS
control features. Default
bit values at reset are shown; if no value is shown, the bit is unde-
fined at reset. Reserved bits are shown on a grey field. These bits
should always be written with zeros.
DWAIT
IOWAIT3
IOWAIT2
IOWAIT1
IOWAIT0
DM(0x3FFE)
WAITSTATE CONTROL
9
8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15 14 13 12 11 10
7
6
5
4
3
2
1
0
WAIT STATE MODE SELECT
0 = NORMAL MODE (PWAIT, DWAIT, IOWAIT0
–
3 = N WAIT STATES, RANGING
FROM 0 TO 7)
1 = 2N + 1 MODE (PWAIT, DWAIT, IOWAIT0
–
3 = 2N + 1 WAIT STATES, RANGING
FROM 0 TO 15)
Figure 6. Wait State Control Register
BMWAIT
CMSSEL
0 = DISABLE
CMS
1 = ENABLE
CMS
(WHERE BIT: 11-IOM, 10-BM, 9-DM, 8-PM)
DM(0x3FE6)
PROGRAMMABLE FLAG AND COMPOSITE SELECT CONTROL
15 14 13 12 11 10
9
8
PFTYPE
0 = INPUT
1 = OUTPUT
1
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
Figure 7. Programmable Flag and Composite Control
Register
RESERVED, ALWAYS
SET TO 0
SPORT0 ENABLE
0 = DISABLE
1 = ENABLE
DM(0x3FFF)
SYSTEM CONTROL
9
8
SPORT1 ENABLE
0 = DISABLE
1 = ENABLE
SPORT1 CONFIGURE
0 = FI, FO,
IRQ0
,
IRQ1
, SCLK
1 = SPORT1
DISABLE
BMS
0 = ENABLE
BMS
1 = DISABLE
BMS
, EXCEPT WHEN MEMORY
STROBES ARE THREE-STATED
PWAIT
PROGRAM MEMORY
WAIT STATES
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
15 14 13 12 11 10
7
6
5
4
3
2
1
0
NOTE: RESERVED BITS ARE SHOWN ON A GRAY FIELD. THESE BITS SHOULD
ALWAYS BE WRITTEN WITH ZEROS.
RESERVED
SET TO 0
Figure 8. System Control Register
I/O Space (Full Memory Mode)
The ADSP-2186M supports an additional external memory
space called I/O space. This space is designed to support simple
connections to peripherals (such as data converters and external
registers) or to bus interface ASIC data registers. I/O space sup-
ports 2048 locations of 16-bit wide data. The lower eleven bits
of the external address bus are used; the upper three bits are
undefined. Two instructions were added to the core ADSP-2100
Family instruction set to read from and write to I/O memory
space. The I/O space also has four dedicated three-bit wait state
registers, IOWAIT0–3, which in combination with the wait state
mode bit, specify up to 15 wait states to be automatically gener-
ated for each of four regions. The wait states act on address
ranges as shown in Table V.
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