參數(shù)資料
型號: ADSP-2186MKCA-300
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號處理
英文描述: CAP 33PF 50V 1206
中文描述: 24-BIT, 37.5 MHz, OTHER DSP, PBGA144
封裝: MINI, BGA-144
文件頁數(shù): 7/40頁
文件大?。?/td> 288K
代理商: ADSP-2186MKCA-300
REV. 0
ADSP-2186M
–7–
Memory Interface Pins
The ADSP-2186M processor can be used in one of two modes: Full Memory Mode, which allows BDMA operation with full exter-
nal overlay memory and I/O capability, or Host Mode, which allows IDMA operation with limited external addressing capabilities.
The operating mode is determined by the state of the Mode C pin during
RESET
and cannot be changed while the processor is running.
The following tables list the active signals at specific pins of the DSP during either of the two operating modes (Full Memory or
Host). A signal in one table shares a pin with a signal from the other table, with the active signal determined by the mode set. For the
shared pins and their alternate signals (e.g., A4/IAD3), refer to the package pinout tables.
Full Memory Mode Pins (Mode C = 0)
Pin Name
# of Pins
I/O
Function
A13:0
D23:0
14
24
O
I/O
Address Output Pins for Program, Data, Byte, and I/O Spaces
Data I/O Pins for Program, Data, Byte, and I/O Spaces (8 MSBs are also
used as Byte Memory Addresses.)
Host Mode Pins (Mode C = 1)
Pin Name
# of Pins
I/O
Function
IAD15:0
A0
D23:8
IWR
IRD
IAL
IS
IACK
16
1
16
1
1
1
1
1
I/O
O
I/O
I
I
I
I
O
IDMA Port Address/Data Bus
Address Pin for External I/O, Program, Data, or Byte Access
1
Data I/O Pins for Program, Data, Byte, and I/O Spaces
IDMA Write Enable
IDMA Read Enable
IDMA Address Latch Pin
IDMA Select
IDMA Port Acknowledge Configurable in Mode D; Open Drain
NOTE
1
In Host Mode, external peripheral addresses can be decoded using the A0,
CMS
,
PMS
,
DMS
, and
IOMS
signals.
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