參數(shù)資料
型號(hào)： ADSP-2186LBST-133
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： DSP Microcomputer
中文描述： 24-BIT, 16.67 MHz, OTHER DSP, PQFP100
封裝： METRIC, PLASTIC, TQFP-100
文件頁(yè)數(shù)： 13/36頁(yè)
文件大?。?/td> 237K
代理商： ADSP-2186LBST-133
ADSP-2186
–13–
REV. A
Target Memory Interface
For your target system to be compatible with the EZ-ICE emu-
lator, it must comply with the memory interface guidelines listed
below.
PM, DM, BM, IOM, and CM
Design a Program Memory (PM), Data Memory (DM), Byte
Memory (BM), I/O Memory (IOM) and Composite Memory
(CM) external interfaces to comply with worst case device timing
requirements and switching characteristics as specified in this
DSP’s data sheet. The performance of the EZ-ICE may approach
published worst case specifications for some memory access
timing requirements and switching characteristics.
Note: If your target does not meet the worst case chip specifica-
tions for memory access parameters, you may not be able to
emulate your circuitry at the desired CLKIN frequency. Depend-
ing on the severity of the specification violation, you may have
trouble manufacturing your system as DSP components statisti-
cally vary in switching characteristics and timing requirements
within published limits.
Restriction: All memory strobe signals on the ADSP-2186 (
RD
,
WR
,
PMS
,
DMS
,
BMS
,
CMS
and
IOMS
) used in your target
system must have 10 k
pull-up resistors connected when the
EZ-ICE is being used. The pull-up resistors are necessary
because there are no internal pull-ups to guarantee their state
during prolonged three-state conditions resulting from typical
EZ-ICE debugging sessions. These resistors may be removed at
your option when the EZ-ICE is not being used.
Target System Interface Signals
When the EZ-ICE board is installed, the performance on some
system signals change. Design your system to be compatible
with the following system interface signal changes introduced by
the EZ-ICE board:
EZ-ICE emulation introduces an 8 ns propagation delay
between your target circuitry and the DSP on the
RESET
signal.
EZ-ICE emulation introduces an 8 ns propagation delay
between your target circuitry and the DSP on the
BR
signal.
EZ-ICE emulation ignores
RESET
and
BR
when single-
stepping.
EZ-ICE emulation ignores
RESET
and
BR
when in Emulator
Space (DSP halted).
EZ-ICE emulation ignores the state of target
BR
in certain
modes. As a result, the target system may take control of the
DSP’s external memory bus only if bus grant (
BG
) is asserted
by the EZ-ICE board’s DSP.
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