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參數(shù)資料
| 型號： | ADSP-2186L1111 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | DSP微機(jī) |
| 文件頁數(shù)： | 11/36頁 |
| 文件大?。?/td> | 237K |
| 代理商： | ADSP-2186L1111 |
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ADSP-2186
–11–
REV. A
IDMA Port Booting
The ADSP-2186 can also boot programs through its Internal
DMA port. If Mode C = 1, Mode B = 0, and Mode A = 1, the
ADSP-2186 boots from the IDMA port. The IDMA feature can
load as much on-chip memory as desired. Program execution is
held off until on-chip program memory location 0 is written to.
Bus Request and Bus Grant
The ADSP-2186 can relinquish control of the data and address
buses to an external device. When the external device requires
access to memory, it asserts the bus request (
BR
) signal. If the
ADSP-2186 is not performing an external memory access, it
responds to the active BR input in the following processor cycle by:
Three-stating the data and address buses and the
PMS
,
DMS
,
BMS
,
CMS
,
IOMS
,
RD
,
WR
output drivers,
Asserting the bus grant (
BG
) signal, and
Halting program execution.
If Go Mode is enabled, the ADSP-2186 will not halt program
execution until it encounters an instruction that requires an
external memory access.
If the ADSP-2186 is performing an external memory access
when the external device asserts the
BR
signal, it will not three-
state the memory interfaces or assert the
BG
signal until the
processor cycle after the access completes. The instruction does
not need to be completed when the bus is granted. If a single
instruction requires two external memory accesses, the bus will
be granted between the two accesses.
When the
BR
signal is released, the processor releases the
BG
signal, reenables the output drivers and continues program
execution from the point at which it stopped.
The bus request feature operates at all times, including when
the processor is booting and when
RESET
is active.
The
BGH
pin is asserted when the ADSP-2186 is ready to
execute an instruction but is stopped because the external bus is
already granted to another device. The other device can release
the bus by deasserting bus request. Once the bus is released, the
ADSP-2186 deasserts
BG
and
BGH
and executes the external
memory access.
Flag I/O Pins
The ADSP-2186 has eight general purpose programmable input/
output flag pins. They are controlled by two memory mapped
registers. The PFTYPE register determines the direction,
1 = output and 0 = input. The PFDATA register is used to read
and write the values on the pins. Data being read from a pin
configured as an input is synchronized to the ADSP-2186’s
clock. Bits that are programmed as outputs will read the value
being output. The PF pins default to input during reset.
In addition to the programmable flags, the ADSP-2186 has five
fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1 and
FL2. FL0-FL2 are dedicated output flags. FLAG_IN and
FLAG_OUT are available as an alternate configuration of
SPORT1.
Note: Pins PF0, PF1 and PF2 are also used for device configu-
ration during reset.
BIASED ROUNDING
A mode is available on the ADSP-2186 to allow biased round-
ing in addition to the normal unbiased rounding. When the
BIASRND bit is set to 0, the normal unbiased rounding opera-
tions occur. When the BIASRND bit is set to 1, biased round-
ing occurs instead of the normal unbiased rounding. When
operating in biased rounding mode all rounding operations with
MR0 set to 0x8000 will round up, rather than only rounding up
odd MR1 values.
For example:
Table VII. Biased Rounding Example
MR Value
Before RND
Biased
RND Result
Unbiased
RND Result
00-0000-8000
00-0001-8000
00-0000-8001
00-0001-8001
00-0000-7FFF
00-0001-7FFF
00-0001-8000
00-0002-8000
00-0001-8001
00-0002-8001
00-0000-7FFF
00-0001-7FFF
00-0000-8000
00-0002-8000
00-0001-8001
00-0002-8001
00-0000-7FFF
00-0001-7FFF
This mode only has an effect when the MR0 register contains
0x8000; all other rounding operations work normally. This
mode allows more efficient implementation of bit-specified
algorithms that use biased rounding, for example the GSM
speech compression routines. Unbiased rounding is preferred
for most algorithms.
Note: BIASRND bit is Bit 12 of the SPORT0 Autobuffer
Control register.
INSTRUCTION SET DESCRIPTION
The ADSP-2186 assembly language instruction set has an alge-
braic syntax that was designed for ease of coding and readabil-
ity. The assembly language, which takes full advantage of the
processor’s unique architecture, offers the following benefits:
The algebraic syntax eliminates the need to remember cryptic
assembler mnemonics. For example, a typical arithmetic add
instruction, such as AR = AX0 + AY0, resembles a simple
equation.
Every instruction assembles into a single, 24-bit word that
can execute in a single instruction cycle.
The syntax is a superset ADSP-2100 Family assembly lan-
guage and is completely source and object code compatible
with other family members. Programs may need to be relo-
cated to utilize on-chip memory and conform to the ADSP-
2186’s interrupt vector and reset vector map.
Sixteen condition codes are available. For conditional jump,
call, return or arithmetic instructions, the condition can be
checked and the operation executed in the same instruction
cycle.
Multifunction instructions allow parallel execution of an
arithmetic instruction with up to two fetches or one write to
processor memory space during a single instruction cycle.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-2186LBCA-160 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 40MHz 40MIPS 144-Pin CSP-BGA 制造商:Rochester Electronics LLC 功能描述:8K/8K 16 BIT DSP 40 MIPS 3.3V MINI BGA - Bulk |
| ADSP2186LBCA-160 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ADSP-2186LBCA-160R | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 40MHz 40MIPS 144-Pin CSP-BGA T/R |
| ADSP-2186LBCA-160R3 | 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer |
| ADSP-2186LBST-115 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 28.8MHz 28.8MIPS 100-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:3.3V 16BIT DSP 28.8MIPS 8KWRDSDM,100TQFP - Bulk |
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