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REV. A
ADSP-2185L
–8–
Table II. Modes of Operations
1
MODE C
2
MODE B
3
MODE A
4
Booting Method
0
0
0
BDMA feature is used to load the first 32 program memory words from the byte memory
space. Program execution is held off until all 32 words have been loaded. Chip is configured
in Full Memory Mode.
5
No Automatic boot operations occur. Program execution starts at external memory location
0. Chip is configured in Full Memory Mode. BDMA can still be used, but the processor does
not automatically use or wait for these operations.
BDMA feature is used to load the first 32 program memory words from the byte memory
space. Program execution is held off until all 32 words have been loaded. Chip is config-
ured in Host Mode.
(REQUIRES ADDITIONAL HARDWARE.)
IDMA feature is used to load any internal memory as desired. Program execution is held off
until internal program memory location 0 is written to. Chip is configured in Host Mode.
5
0
1
0
1
0
0
1
0
1
NOTES
1
All mode pins are recognized while
RESET
is active (low).
2
When Mode C = 0, Full Memory enabled. When Mode C = 1, Host Memory Mode enabled.
3
When Mode B = 0, Auto Booting enabled. When Mode B = 1, no Auto Booting.
4
When Mode A = 0, BDMA enabled. When Mode A = 1, IDMA enabled.
5
Considered as standard operating settings. Using these configurations allows for easier design and better memory management.
MEMORY ARCHITECTURE
The ADSP-2185L provides a variety of memory and peripheral
interface options. The key functional groups are Program
Memory, Data Memory, Byte Memory, and I/O. Refer to the
following figures and tables for PM and DM memory alloca-
tions in the ADSP-2185L.
PROGRAM MEMORY
Program Memory (Full Memory Mode)
is a 24-bit-wide
space for storing both instruction opcodes and data. The
ADSP-2185L has 16K words of Program Memory RAM on
chip, and the capability of accessing up to two 8K external
memory overlay spaces using the external data bus
.
Program Memory (Host Mode)
allows access to all internal
memory. External overlay access is limited by a single external
address line (A0). External program execution is not available in
host mode due to a restricted data bus that is 16-bits wide only.
Table III. PMOVLAY Bits
PMOVLAY Memory
A13
A12:0
0
1
Internal
External
Overlay 1
Not Applicable
0
Not Applicable
13 LSBs of Address
Between 0x2000
and 0x3FFF
13 LSBs of Address
Between 0x2000
and 0x3FFF
2
External
Overlay 2
1
ACCESSIBLE WHEN
PMOVLAY = 2
ACCESSIBLE WHEN
PMOVLAY = 1
ALWAYS
ACCESSIBLE
AT ADDRESS
0x0000 – 0x1FFF
ACCESSIBLE WHEN
PMOVLAY = 0
PM (MODE B = 0)
INTERNAL
MEMORY
EXTERNAL
MEMORY
0x2000–
0x3FFF
0x2000–
0x3FFF
2
0x2000–
0x3FFF
2
8K INTERNAL
PMOVLAY = 0
8K EXTERNAL
PROMODE B = 1
ADDRESS
0x3FFF
0x2000
0x1FFF
0x0000
8K INTERNAL
PMOVLAY = 0
8K EOR
PMOVLAY = 1 OR 2
0x3FFF
0x2000
0x1FFF
8K INTERNAL
0x0000
PROGRAM MEMORY
MODE B = 0
ADDRESS
ACCESSIBLE WHEN
PMOVLAY = 0
INTERNAL
MEMORY
EXTERNAL
0x2000–
0x3FFF
0x0000–
0x1FFF
2
PM (MODE B = 1)
1
RESERVED
1
WHEN MODE B = 1, PMOVLAY MUST BE SET TO 0
2
SEE TABLE III FOR PMOVLAY BITS
ACCESSIBLE WHEN
PMOVLAY = 0
RESERVED
Figure 4. Program Memory