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參數(shù)資料
| 型號： | ADSP-2185MKSTZ-300 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/40頁 |
| 文件大小： | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 100-LQFP |
| 標準包裝： | 1 |
| 系列： | ADSP-21xx |
| 類型： | 定點 |
| 接口： | 主機接口，串行端口 |
| 時鐘速率： | 75MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 80kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 2.50V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應商設備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
| 其它名稱： | ADSP-2185MKSTZ300 |
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REV. 0
ADSP-2185M
–13–
Data Memory
Data Memory (Full Memory Mode) is a 16-bit-wide space used
for the storage of data variables and for memory-mapped control
registers. The ADSP-2185M has 16K words on Data Memory
RAM on-chip. Part of this space is used by 32 memory-mapped
registers. Support also exists for up to two 8K external memory
overlay spaces through the external data bus. All internal accesses
ACCESSIBLE WHEN
DMOVLAY = 2
ACCESSIBLE WHEN
DMOVLAY = 1
0x0000 – 0x1FFF1
EXTERNAL
MEMORY
32 MEMORY
MAPPED
REGISTERS
0x3FFF
INTERNAL
8160 WORDS
0x0000
DATA MEMORY
ADDR
0x3FE0
8K INTERNAL
DMOVLAY = 0
OR
EXTERNAL 8K
DMOVLAY = 1, 2
0x1FFF
0x3FDF
0x2000
ACCESSIBLE WHEN
DM OVLAY = 0
0x0000 – 0x1FFF
DATA MEMORY
ALWAYS
ACCESSIBLE
AT ADDRESS
0x2000 – 0x3FFF
NOTE:
1SEE TABLE IV FOR DMOVAY BITS
Figure 5. Data Memory Map
complete in one cycle. Accesses to external memory are timed
using the wait states specified by the DWAIT register and the
wait state mode bit.
Data Memory (Host Mode) allows access to all internal memory.
External overlay access is limited by a single external address
line (A0).
Table IV. DMOVLAY Bits
DMOVLAY
Memory
A13
A12:0
0
Internal
Not Applicable
1
External Overlay 1
0
13 LSBs of Address Between 0x2000 and 0x3FFF
2
External Overlay 2
1
13 LSBs of Address Between 0x2000 and 0x3FFF
Memory Mapped Registers (New to the ADSP-2185M)
The ADSP-2185M has three memory mapped registers that differ
from other ADSP-21xx Family DSPs. The slight modifications
to these registers (Wait State Control, Programmable Flag and
Composite Select Control, and System Control) provide the
ADSP-2185M’s wait state and
BMS control features. Default
bit values at reset are shown; if no value is shown, the bit is unde-
fined at reset. Reserved bits are shown on a grey field. These bits
should always be written with zeros.
DWAIT
IOWAIT3
IOWAIT2
IOWAIT1
IOWAIT0
DM(0 3FFE)
WAITSTATE CONTROL
11
1
11
111
1
15 14 13 12 11 10
9
8
7
6
5
43210
WAIT STATE MODE SELECT
0 = NORMAL MODE (PWAIT, DWAIT, IOWAIT0–3 = N WAIT STATES, RANGING
FROM 0 TO 7)
1 = 2N + 1 MODE (PWAIT, DWAIT, IOWAIT0–3 = 2N + 1 WAIT STATES, RANGING
FROM 0 TO 15)
Figure 6. Wait State Control Register
BMWAIT
CMSSEL
0 = DISABLE
CMS
1 = ENABLE
CMS
DM(0x3FE6)
PROGRAMMABLE FLAG AND COMPOSITE SELECT CONTROL
PFTYPE
0 = INPUT
1 = OUTPUT
(WHERE BIT: 11-IOM, 10-BM, 9-DM, 8-PM)
11
1
0
11
000
0
15 14 13 12 11 10
9
8
7
6
5
43210
Figure 7. Programmable Flag and Composite Control
Register
RESERVED, ALWAYS
SET TO 0
SPORT0 ENABLE
0 = DISABLE
1 = ENABLE
DM(0x3FFF)
SYSTEM CONTROL
SPORT1 ENABLE
0 = DISABLE
1 = ENABLE
SPORT1 CONFIGURE
0 = FI, FO,
IRQ0, IRQ1, SCLK
1 = SPORT1
DISABLE
BMS
0 = ENABLE
BMS
1 = DISABLE
BMS, EXCEPT WHEN MEMORY
STROBES ARE THREE-STATED
PWAIT
PROGRAM MEMORY
WAIT STATES
00
0
1
00
000
0
1
15 14 13 12 11 10
9
8
7
6
5
43210
NOTE: RESERVED BITS ARE SHOWN ON A GRAY FIELD. THESE BITS SHOULD
ALWAYS BE WRITTEN WITH ZEROS.
RESERVED
SET TO 0
Figure 8. System Control Register
I/O Space (Full Memory Mode)
The ADSP-2185M supports an additional external memory
space called I/O space. This space is designed to support simple
connections to peripherals (such as data converters and external
registers) or to bus interface ASIC data registers. I/O space sup-
ports 2048 locations of 16-bit wide data. The lower eleven bits
of the external address bus are used; the upper three bits are
undefined. Two instructions were added to the core ADSP-2100
Family instruction set to read from and write to I/O memory
space. The I/O space also has four dedicated three-bit wait state
registers, IOWAIT0–3, which in combination with the wait state
mode bit, specify up to 15 wait states to be automatically gener-
ated for each of four regions. The wait states act on address
ranges as shown in Table V.
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| ADSP-2185N | 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer |
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| ADSP-2185NBSTZ-320 | 功能描述:IC DSP CONTROLLER 16BIT 100LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:ADSP-21xx 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
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