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參數(shù)資料
| 型號： | ADSP-2185MBSTZ-266 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 100-LQFP |
| 標準包裝： | 1 |
| 系列： | ADSP-21xx |
| 類型： | 定點 |
| 接口： | 主機接口，串行端口 |
| 時鐘速率： | 66MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 80kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 2.50V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
| 其它名稱： | ADSP-2185MBSTZ266 ADSP-2185MBSTZ266-ND |
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REV. 0
–12–
ADSP-2185M
Active Configuration
Active Configuration involves the use of a three-statable external
driver connected to the Mode C pin. A driver’s output enable
should be connected to the DSP’s
RESET signal such that it
only drives the PF2 pin when
RESET is active (low). When
RESET is deasserted, the driver should three-state, thus allow-
ing full use of the PF2 pin as either an input or output. To
minimize power consumption during power-down, configure
the programmable flag as an output when connected to a three-
stated buffer. This ensures that the pin will be held at a constant
level, and will not oscillate should the three-state driver’s level
hover around the logic switching point.
IACK Configuration
Mode D = 0 and in host mode:
IACK is an active, driven signal
and cannot be “wire OR’d.”
Mode D = 1 and in host mode:
IACK is an open drain and
requires an external pull-down, but multiple
IACK pins can be
“wire OR’d” together.
MEMORY ARCHITECTURE
The ADSP-2185M provides a variety of memory and peripheral
interface options. The key functional groups are Program Memory,
Data Memory, Byte Memory, and I/O. Refer to the following
figures and tables for PM and DM memory allocations in the
ADSP-2185M.
Program Memory
Program Memory (Full Memory Mode) is a 24-bit-wide
space for storing both instruction opcodes and data. The ADSP-
2185M has 16K words of Program Memory RAM on chip, and
the capability of accessing up to two 8K external memory over-
lay spaces using the external data bus.
Program Memory (Host Mode) allows access to all internal
memory. External overlay access is limited by a single external
address line (A0). External program execution is not available in
host mode due to a restricted data bus that is 16 bits wide only.
ACCESSIBLE WHEN
PMOVLAY = 0
0x0000 –
0x1FFF2
EXTERNAL
MEMORY
0x0000 –
0x1FFF2
RESERVED
ACCESSIBLE WHEN
PMOVLAY = 2
0x2000 –
0x3FFF2
0x2000 –
0x3FFF2
EXTERNAL
MEMORY
ACCESSIBLE WHEN
PMOVLAY = 1
ACCESSIBLE WHEN
PMOVLAY = 0
0x2000 –
0x3FFF
PM (MODE B = 0)
ALWAYS
ACCESSIBLE
AT ADDRESS
0x0000 – 0x1FFF
PM (MODE B = 1)1
RESERVED
NOTES:
1WHEN MODE B = 1, PMOVLAY MUST BE SET TO 0
2SEE TABLE III FOR PMOVLAY BITS
ACCESSIBLE WHEN
PMOVLAY = 0
0x2000 –
0x3FFF
8K
INTERNAL
0x0000
8K INTERNAL
PMOVLAY = 0
OR
8K EXTERNAL
PMOVLAY = 1, 2
0x1FFF
0x2000
PROGRAM MEMORY
MODE B = 0
ADDRESS
0x3FFF
8K
EXTERNAL
0x0000
8K INTERNAL
PMOVLAY = 0
0x1FFF
0x2000
PROGRAM MEMORY
MODE B = 1
ADDRESS
Figure 4. Program Memory
Table III. PMOVLAY Bits
PMOVLAY
Memory
A13
A12:0
0
Internal
Not Applicable
1
External Overlay 1
0
13 LSBs of Address Between 0x2000 and 0x3FFF
2
External Overlay 2
1
13 LSBs of Address Between 0x2000 and 0x3FFF
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