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參數(shù)資料
| 型號： | ADSP-2185BST-133 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | 16-BIT, 16.67 MHz, OTHER DSP, PQFP100 |
| 封裝： | METRIC, PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 7/31頁 |
| 文件大?。?/td> | 223K |
| 代理商： | ADSP-2185BST-133 |
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ADSP-2185L
–7–
REV. A
1/2xOR
CRYSTAL
SERIAL
SERIAL
SCLK1
RFS1 OR
IRQ0
IRQ1
TFS1 OR
SCLK0
SPORT0
A0-A21
DATA
CS
BYTE
MEMORY
I/O SPACE
(PERIPHERALS)
2048 LOCATIONS
CS
DATA
ADDR
DATA
ADDR
OVERLAY
MEMORY
PM TWO 8K
DM TWO 8K
D
23-0
A
13-0
D
23-8
A
10-0
D
15-8
D
23-16
A
13-0
14
24
FL0-2
CLKIN
XTAL
ADDR13-0
DATA23-0
BMS
IOMS
PMS
DMS
CMS
BR
BBG
PWD
PWDACK
ADSP-2185L
1/2x OR
CRYSTAL
SERIAL
ISYOR
m
CONTROLLER
16
1
16
SCLK1
IRQ0
RFS1 OR
SCLK0
SPORT0
IAD15-0
IDMA PORT
/D6
IRD
/D7
IS
IACK
/D3
FL0-2
PF3
CLKIN
XTAL
A0
DATA23-8
BMS
IOMS
PMS
DMS
CMS
BR
BBG
ADSP-2185L
IRQ2
/PF4
IRQE
IRQL0
/PF5
HOST MEMORY MODE
/PF4
IRQ2
/PF5
IRQL0
/PF6
PF2 [MODE C]
PF1 [MODE B]
PF0 [MODE A]
FULL MEMORY MODE
SERIAL
WR
RD
WR
RD
PWD
PWDACK
PF2 [MODE C]
PF1 [MODE B]
PF0 [MODE A]
Figure 2. ADSP-2185L Basic System Configuration
CLKIN
CLKOUT
XTAL
DSP
Figure 3. External Crystal Connections
Reset
The
RESET
signal initiates a master reset of the ADSP-2185L.
The
RESET
signal must be asserted during the power-up se-
quence to assure proper initialization.
RESET
during initial
power-up must be held long enough to allow the internal clock
to stabilize. If
RESET
is activated any time after power-up, the
clock continues to run and does not require stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid V
DD
is ap-
plied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum
of 2000 CLKIN cycles ensures that the PLL has locked, but
does not include the crystal oscillator start-up time. During this
power-up sequence the
RESET
signal should be held low. On
any subsequent resets, the
RESET
signal must meet the mini-
mum pulsewidth specification, t
RSP
.
The
RESET
input contains some hysteresis; however, if an
RC circuit is used to generate the
RESET
signal, an external
Schmidt trigger is recommended.
The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts and clears the MSTAT
register. When
RESET
is released, if there is no pending bus
request and the chip is configured for booting, the boot-loading
sequence is performed. The first instruction is fetched from
on-chip program memory location 0x0000 once boot loading
completes.
MODES OF OPERATION
Table II summarizes the ADSP-2185L memory modes.
Setting Memory Mode
Memory Mode selection for the ADSP-2185L is made during
chip reset through the use of the Mode C pin. This pin is multi-
plexed with the DSP’s PF2 pin, so care must be taken in how
the mode selection is made. The two methods for selecting the
value of Mode C are active and passive.
Passive configuration
involves the use a pull-up or pull-down
resistor connected to the Mode C pin. To minimize power con-
sumption, or if the PF2 pin is to be used as an output in the
DSP application, a weak pull-up or pull-down, on the order of
100 k
, can be used. This value should be sufficient to pull the
pin to the desired level and still allow the pin to operate as
a programmable flag output without undue strain on the
processor’s output driver. For minimum power consumption
during power-down, reconfigure PF2 to be an input, as the
pull-up or pull-down will hold the pin in a known state, and will
not switch.
Active configuration
involves the use of a three-statable exter-
nal driver connected to the Mode C pin. A driver’s output en-
able should be connected to the DSP’s
RESET
signal such that
it only drives the PF2 pin when
RESET
is active (low). When
RESET
is deasserted, the driver should three-state, thus allow-
ing full use of the PF2 pin as either an input or output. To
minimize power consumption during power-down, configure
the programmable flag as an output when connected to a three-
stated buffer. This ensures that the pin will be held at a con-
stant level and not oscillate should the three-state driver’s level
hover around the logic switching point.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-2185BSTZ-133 | 功能描述:IC DSP CONTROLLER 16BIT 100TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:ADSP-21xx 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-2185BSTZ-133 | 制造商:Analog Devices 功能描述:IC 16-BIT MICROCOMPUTER |
| ADSP-2185KST-115 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 28.8MHz 28.8MIPS 100-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:DSP,5V,28MHZ,32K WORD RAM, 100TQFP - Bulk |
| ADSP2185KST133 | 制造商:Analog Devices 功能描述: |
| ADSP-2185KST-133 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 33.3MHz 33.3MIPS 100-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:DSP,5V,33MHZ,32K WORD RAM, 100TQFP - Bulk 制造商:Analog Devices 功能描述:Digital Signal Processor IC |
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