Timing Requirements: tCKI C" />
參數(shù)資料
型號: ADSP-2183KCA-210
廠商: Analog Devices Inc
文件頁數(shù): 6/31頁
文件大小: 0K
描述: IC DSP CONTROLLER 16BIT 144MBGA
標(biāo)準(zhǔn)包裝: 1
系列: ADSP-21xx
類型: 定點(diǎn)
接口: 同步串行端口(SSP)
時(shí)鐘速率: 52MHz
非易失內(nèi)存: 外部
芯片上RAM: 80kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 3.30V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 144-LFBGA
供應(yīng)商設(shè)備封裝: 144-迷你型BGA
包裝: 托盤
ADSP-2183
–14–
REV. C
Parameter
Min
Max
Unit
Clock Signals and Reset
Timing Requirements:
tCKI
CLKIN Period
38
100
ns
tCKIL
CLKIN Width Low
15
ns
tCKIH
CLKIN Width High
15
ns
Switching Characteristics:
tCKL
CLKOUT Width Low
0.5tCK – 7
ns
tCKH
CLKOUT Width High
0.5tCK – 7
ns
tCKOH
CLKIN High to CLKOUT High
0
20
ns
Control Signals
Timing Requirement:
tRSP
RESET Width Low
5tCK
1
ns
NOTE
1Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
CLKIN
CLKOUT
tCKIL
tCKOH
tCKH
tCKL
tCKIH
tCKI
Figure 8. Clock Signals
Parameter
Min
Max
Unit
Interrupts and Flag
Timing Requirements:
tIFS
IRQx, FI, or PFx Setup before CLKOUT Low 1, 2, 3, 4
0.25tCK + 15
ns
tIFH
IRQx, FI, or PFx Hold after CLKOUT High 1, 2, 3, 4
0.25tCK
ns
Switching Characteristics:
tFOH
Flag Output Hold after CLKOUT Low5
0.5tCK – 7
ns
tFOD
Flag Output Delay from CLKOUT Low
5
0.5tCK + 6
ns
NOTES
1If
IRQx and FI inputs meet t
IFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on
the following cycle. (Refer to Interrupt Controller Operation in the Program Control chapter of the User’s Manual for further information on interrupt servicing.)
2Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
3
IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQE.
4PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.
5Flag outputs = PFx, FL0, FL1, FL2, Flag_out4.
tFOD
tFOH
tIFS
CLKOUT
FLAG
OUTPUTS
IRQx
FI
PFx
tIFH
Figure 9. Interrupts and Flags
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