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參數(shù)資料
| 型號： | ADSP-2181KST-160 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | 24-BIT, 20 MHz, OTHER DSP, PQFP128 |
| 封裝： | METRIC, PLASTIC, TQFP-128 |
| 文件頁數(shù)： | 2/32頁 |
| 文件大?。?/td> | 290K |
| 代理商： | ADSP-2181KST-160 |
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REV. D
ADSP-2181
–2–
T his takes place while the processor continues to:
Receive and transmit data through the two serial ports
Receive and/or transmit data through the internal DMA port
Receive and/or transmit data through the byte DMA port
Decrement timer
Development System
T he ADSP-2100 Family Development Software, a complete
set of tools for software and hardware system development,
supports the ADSP-2181. T he System Builder provides a high
level method for defining the architecture of systems under
development. T he Assembler has an algebraic syntax that is easy
to program and debug. T he L inker combines object files into
an executable file. T he Simulator provides an interactive
instruction-level simulation with a reconfigurable user interface
to display different portions of the hardware environment. A
PROM Splitter generates PROM programmer compatible files.
T he C Compiler, based on the Free Software Foundation’s
GNU C Compiler, generates ADSP-2181 assembly source
code. T he source code debugger allows programs to be cor-
rected in the C environment. T he Runtime Library includes over
100 ANSI-standard mathematical and DSP-specific functions.
T he EZ-K IT Lite is a hardware/software kit offering a complete
development environment for the entire ADSP-21xx family: an
ADSP-2181 evaluation board with PC monitor software plus
Assembler, Linker, Simulator, and PROM Splitter software.
T he ADSP-218x EZ-K IT Lite is a low-cost, easy to use hard-
ware platform on which you can quickly get started with your
DSP software design. T he EZ-K IT Lite includes the following
features:
33 MHz ADSP-2181
Full 16-bit Stereo Audio I/O with AD1847 SoundPort
Codec
RS-232 Interface to PC with Windows 3.1 Control Software
Stand-Alone Operation with Socketed EPROM
EZ-ICE
Connector for Emulator Control
DSP Demo Programs
T he ADSP-218x EZ-ICE
Emulator aids in the hardware debug-
ging of ADSP-218x systems. T he emulator consists of hard-
ware, host computer resident software and the target board
connector. T he ADSP-218x integrates on-chip emulation sup-
port with a 14-pin ICE-Port interface. T his interface provides a
simpler target board connection requiring fewer mechanical
clearance considerations than other ADSP-2100 Family EZ-ICEs.
T he ADSP-218x device need not be removed from the target
system when using the EZ-ICE, nor are any adapters needed. Due
to the small footprint of the EZ-ICE
connector, emulation can be
supported in final board designs.
T he EZ-ICE
performs a full range of functions, including:
In-target operation
Up to 20 breakpoints
Single-step or full-speed operation
Registers and memory values can be examined and altered
PC upload and download functions
Instruction-level emulation of program booting and execution
Complete assembly and disassembly of instructions
C source-level debugging
See the Designing An EZ-ICE-Compatible T arget System sec-
tion of this data sheet for exact specifications of the EZ-ICE target
board connector.
Additional Information
T his data sheet provides a general overview of ADSP-2181
functionality. For additional information on the architecture and
instruction set of the processor, refer to the
ADSP-2100 Family
User’s Manual, Third Edition
. For more information about the
development tools, refer to the
ADSP-2100 Family Development
Tools Data Sheet
.
ARCHIT E CT URE OVE RVIE W
T he ADSP-2181 instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single pro-
cessor cycle. T he ADSP-2181 assembly language uses an alge-
braic syntax for ease of coding and readability. A comprehensive
set of development tools supports program development.
Figure 1 is an overall block diagram of the ADSP-2181. T he
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC) and the shifter. T he
computational units process 16-bit data directly and have provi-
sions to support multiprecision computations. T he ALU per-
forms a standard set of arithmetic and logic operations; division
primitives are also supported. T he MAC performs single-cycle
multiply, multiply/add and multiply/subtract operations with
40 bits of accumulation. T he shifter performs logical and arith-
metic shifts, normalization, denormalization and derive expo-
nent operations. T he shifter can be used to efficiently implement
numeric format control including multiword and block floating-
point representations.
T he internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these computa-
tional units. T he sequencer supports conditional jumps, subroutine
calls and returns in a single cycle. With internal loop counters and
loop stacks, the ADSP-2181 executes looped code with zero over-
head; no explicit jump instructions are required to maintain loops.
T wo data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four possible modify registers. A length value may be associated
with each pointer to implement automatic modulo addressing
for circular buffers.
Efficient data transfer is achieved with the use of five internal
buses:
Program Memory Address (PMA) Bus
Program Memory Data (PMD) Bus
Data Memory Address (DMA) Bus
Data Memory Data (DMD) Bus
Result (R) Bus
T he two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.
Program memory can store both instructions and data, permit-
ting the ADSP-2181 to fetch two operands in a single cycle,
one from program memory and one from data memory. T he
EZ-ICE and SoundPort are registered trademarks of Analog Devices, Inc.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADSP-2181 | ADSP-2100 Family DSP Microcomputers |
| ADSP-2181BST-115 | DSP Microcomputer |
| ADSP-2181BST-133 | DSP Microcomputer |
| ADSP2181 | DSP Microcomputer |
| ADSP-2183KST-115 | DSP Microcomputer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-2181KST-160R | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 40MHz 40MIPS 128-Pin LQFP T/R |
| ADSP-2181KSTZ-115 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| ADSP-2181KSTZ-133 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 33.3MHz 33.3MIPS 128-Pin LQFP 制造商:Analog Devices 功能描述:MICROCOMPUTER 16BIT 33MIPS SMD |
| ADSP-2181KSTZ-160 | 功能描述:IC DSP CONTROLLER 16BIT 128TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:ADSP-21xx 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-2181KSZ-133 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:MICROCOMPUTER 16BIT 33MIPS SMD |
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