參數(shù)資料
型號(hào): ADSP-2171
廠商: Analog Devices, Inc.
英文描述: DSP Microcomputer(DSP 微計(jì)算機(jī))
中文描述: 微機(jī)的DSP(數(shù)字信號(hào)處理器微計(jì)算機(jī))
文件頁(yè)數(shù): 34/52頁(yè)
文件大?。?/td> 685K
代理商: ADSP-2171
REV. A
–34–
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2173
Parameter
Min
Max
Unit
Interrupts and Flags
T iming Requirement:
t
IFS
t
IFH
IRQx
or FI Setup before CLK OUT Low
1, 2, 3
IRQx
or FI Hold after CLK OUT High
1, 2, 3
0.25t
CK
+ 23
0.25t
CK
ns
ns
Switching Characteristic:
t
FOH
t
FOD
Flag Output Hold after CLK OUT Low
4
Flag Output Delay from CLK OUT Low
4
0.5t
CK
– 10
ns
ns
0.5t
CK
+ 5
NOT ES
1
If
IRQx
and FI inputs meet t
and t
setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on
the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the User’s Manual for further information on interrupt servicing.)
2
Edge-sensitive interrupts require pulse widths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
3
IRQx
=
IRQ0
,
IRQ1
, and
IRQ2
.
4
Flag Output = FL0, FL1, FL2, and FO.
CLKOUT
FLAG
OUTPUTS
IRQ
x
FI
t
IFS
t
FOD
t
FOH
t
IFH
Figure 25. Interrupts and Flags
相關(guān)PDF資料
PDF描述
ADSP-2172 DSP Microcomputer(DSP 微計(jì)算機(jī))
ADSP-2173 DSP Microcomputer(DSP 微計(jì)算機(jī))
ADSP-2181BS-115 DSP Microcomputer
ADSP-2181BS-133 DSP Microcomputer
ADSP-2181KS-115 DSP Microcomputer
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