Figure 31 shows the default I
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Rev. B
|
Page 46 of 68
|
March 2013
Figure 31 shows the default I2S-justified mode. The frame sync
is low for the left channel and HI for the right channel. Data is
valid on the rising edge of serial clock. The MSB is left-justified
to the frame sync transition but with a delay.
Figure 32 shows the left-justified mode. The frame sync is high
for the left channel and low for the right channel. Data is valid
on the rising edge of serial clock. The MSB is left-justified to the
frame sync transition with no delay.
Table 45. S/PDIF Transmitter I2S Mode
Parameter
Nominal
Unit
Timing Requirement
tI2SD
Frame Sync to MSB Delay in I2S Mode
1
SCLK
Figure 31. I2S-Justified Mode
MSB
LEFT/RIGHT CHANNEL
LSB
MSB鈥�1 MSB鈥�2
LSB+2
LSB+1
DAI_P20鈥�1
FS
DAI_P20鈥�1
SCLK
DAI_P20鈥�1
SDATA
tI2SD
Table 46. S/PDIF Transmitter Left-Justified Mode
Parameter
Nominal
Unit
Timing Requirement
tLJD
Frame Sync to MSB Delay in Left-Justified Mode
0
SCLK
Figure 32. Left-Justified Mode
MSB
LEFT/RIGHT CHANNEL
LSB
MSB鈥�1 MSB鈥�2
LSB+2
LSB+1
DAI_P20鈥�1
FS
DAI_P20鈥�1
SCLK
DAI_P20鈥�1
SDATA
tLJD
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