參數(shù)資料
型號(hào): ADSP-21369KSWZ-5A
廠商: Analog Devices Inc
文件頁(yè)數(shù): 39/64頁(yè)
文件大小: 0K
描述: IC DSP 32BIT 366MHZ 208LQFP
標(biāo)準(zhǔn)包裝: 1
系列: SHARC®
類型: 浮點(diǎn)
接口: DAI,DPI
時(shí)鐘速率: 366MHz
非易失內(nèi)存: ROM(768 kB)
芯片上RAM: 256kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 208-LQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 208-LQFP-EP(28x28)
包裝: 托盤(pán)
Rev. F
|
Page 44 of 64
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October 2013
S/PDIF Transmitter
Serial data input to the S/PDIF transmitter can be formatted as
left justified, I2S, or right justified with word widths of 16, 18, 20,
or 24 bits. The following sections provide timing for the
transmitter.
S/PDIF Transmitter—Serial Input Waveforms
Figure 31 shows the right-justified mode. LRCLK is high for the
left channel and low for the right channel. Data is valid on the
rising edge of SCLK. The MSB is delayed 12-bit clock periods
(in 20-bit output mode) or 16-bit clock periods (in 16-bit output
mode) from an LRCLK transition, so that when there are 64
SCLK periods per LRCLK period, the LSB of the data is right-
justified to the next LRCLK transition.
Figure 32 shows the default I2S-justified mode. LRCLK is low
for the left channel and high for the right channel. Data is valid
on the rising edge of SCLK. The MSB is left-justified to an
LRCLK transition but with a single SCLK period delay.
Figure 31. Right-Justified Mode
MSB
LEFT/RIGHT CHANNEL
LSB
MSB–1 MSB–2
LSB+2
LSB+1
DAI_P20–1
FS
DAI_P20–1
SCLK
DAI_P20–1
SDATA
tRJD
Figure 32. I2S-Justified Mode
MSB
LEFT/RIGHT CHANNEL
LSB
MSB–1 MSB–2
LSB+2
LSB+1
DAI_P20–1
FS
DAI_P20–1
SCLK
DAI_P20–1
SDATA
tI2SD
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