
Rev. PrA
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Page 22 of 54
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September 2004
ADSP-21365/6
Preliminary Technical Data
Timer WDTH_CAP Timing
The following timing specification applies to Timer0, Timer1,
and Timer2 in WDTH_CAP (pulse width count and capture)
mode. Timer signals are routed to the DAI_P20–1 pins through
the SRU. Therefore, the timing specification provided below are
valid at the DAI_P20–1 pins.
DAI Pin to Pin Direct Routing
For direct pin connections only (for example DAI_PB01_I to
DAI_PB02_O).
Table 16. Timer Width Capture Timing
Parameter
Timing Requirement
t
PWI
Min
Max
Unit
Timer Pulse Width
2 t
PCLK
2(2
31
– 1) t
PCLK
ns
Figure 13. Timer Width Capture Timing
DAI_P20-1
(TIMER2-0)
t
PWI
Table 17. DAI Pin to Pin Routing
Parameter
Timing Requirement
t
DPIO
Min
Max
Unit
Delay DAI Pin Input Valid to DAI Output Valid
1.5
10
ns
Figure 14. DAI Pin to Pin Direct Routing
DAI_Pn
t
DPIO
DAI_Pm