參數(shù)資料
型號(hào)： ADSP-21365SCSQ-ENG
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： SHARC Processor
中文描述： 16-BIT, 55.55 MHz, OTHER DSP, PQFP144
封裝： MS-026BFB-HD, HSLQFP-144
文件頁(yè)數(shù)： 33/54頁(yè)
文件大?。?/td> 559K
代理商： ADSP-21365SCSQ-ENG
ADSP-21365/6
Preliminary Technical Data
Rev. PrA
|
Page 33 of 54
|
September 2004
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in
Table 29
. PDAP is the parallel mode operation of channel 0 of
the IDP. For details on the operation of the IDP, see the IDP
chapter of the
ADSP-2136x SHARC Processor Hardware Refer-
ence
. Note that the most significant 16 bits of external PDAP
data can be provided through either the parallel port AD15–0 or
the DAI_P20–5 pins. The remaining 4 bits can only be sourced
through DAI_P4–1. The timing below is valid at the
DAI_P20–1 pins or at the AD15–0 pins.
Table 29. Parallel Data Acquisition Port (PDAP)
Parameter
Timing Requirements
t
SPCLKEN
1
t
HPCLKEN
1
t
PDSD
1
t
PDHD
1
t
PDCLKW
t
PDCLK
Min
Max
Unit
PDAP_CLKEN Setup Before PDAP_CLK Sample Edge
PDAP_CLKEN Hold After PDAP_CLK Sample Edge
PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge
PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge
Clock Width
Clock Period
2.5
2.5
2.5
2.5
7
24
ns
ns
ns
ns
ns
ns
Switching Characteristics
t
PDHLDD
t
PDSTRB
1
Source pins of DATA are ADDR7–0, DATA7–0, or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.
Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word
PDAP Strobe Pulse Width
2 × t
CCLK
1 × t
CCLK
– 1
ns
ns
Figure 24. PDAP Timing
DAI_P20-1
(PDAP_CLK)
SAMPLE EDGE
t
PDSD
t
PDHD
t
SPCLKEN
t
HPCLKEN
t
PDCLKW
DATA
DAI_P20-1
(PDAP_CLKEN)
t
PDSTRB
t
PDHLDD
DAI_P20-1
(PDAP_STROBE)
t
PDCLK
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