參數(shù)資料
Rev. PrA
|
Page 42 of 54
|
September 2004
ADSP-21365/6
Preliminary Technical Data
JTAG Test Access Port and Emulation
Table 38. JTAG Test Access Port and Emulation
Parameter
Timing Requirements
t
TCK
t
STAP
t
HTAP
t
SSYS
1
t
HSYS
1
t
TRSTW
Min
Max
Unit
TCK Period
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK Low
System Inputs Hold After TCK Low
TRST Pulse Width
t
CK
5
6
7
18
4t
CK
ns
ns
ns
ns
ns
ns
Switching Characteristics
t
DTDO
t
DSYS
2
1
System Inputs = AD15–0, SPIDS, CLKCFG1–0, RESET, BOOTCFG1–0, MISO, MOSI, SPICLK, DAI_Px, FLAG3–0.
2
System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15–0, RD, WR, FLAG3–0, CLKOUT, EMU, ALE.
TDO Delay from TCK Low
System Outputs Delay After TCK Low
7
10
ns
ns
Figure 35. IEEE 1149.1 JTAG Test Access Port
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
t
STAP
t
TCK
t
HTAP
t
DTDO
t
SSYS
t
HSYS
t
DSYS
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