參數(shù)資料
型號: ADSP-21364SBSQZENG
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號處理
英文描述: SHARC Processor
中文描述: 16-BIT, 55.55 MHz, OTHER DSP, PQFP144
封裝: LEAD FREE, MS-026BFB-HD, HSLQFP-144
文件頁數(shù): 40/52頁
文件大?。?/td> 853K
代理商: ADSP-21364SBSQZENG
Rev. PrB
|
Page 40 of 52
|
September 2004
ADSP-21364
Preliminary Technical Data
SPI Interface—Master
Table 36. SPI Interface Protocol — Master Switching and Timing Specifications
Parameter
Timing Requirements
t
SSPIDM
t
HSPIDM
Min
Max
Unit
Data Input Valid to SPICLK Edge (Data Input Set-up Time)
SPICLK Last Sampling Edge to Data Input Not Valid
8
2
ns
ns
Switching Characteristics
t
SPICLKM
t
SPICHM
t
SPICLM
t
DDSPIDM
t
HDSPIDM
t
SDSCIM
t
HDSM
t
SPITDM
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPICLK Edge to Data Out Valid (Data Out Delay Time)
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
FLAG3–0IN (SPI Device Select) Low to First SPICLK Edge
Last SPICLK edge to FLAG3–0IN High
Sequential Transfer Delay
8 × t
PCLK
4 × t
PCLK
4 × t
PCLK
– 2
ns
ns
ns
0
2
4 × t
PCLK
– 2
4 × t
PCLK
– 1
4 × t
PCLK
– 1
ns
ns
ns
ns
Figure 33. SPI Master Timing
LSB
VALID
MSB
VALID
t
SSPIDM
t
HSPIDM
t
HDSPIDM
LSB
MSB
t
HSSPIDM
t
DDSPIDM
MOSI
(OUTPUT)
MISO
(INPUT)
FLAG3-0
(OUTPUT)
SPICLK
(CP = 0)
(OUTPUT)
SPICLK
(CP = 1)
(OUTPUT)
t
SPICHM
t
SPICLM
t
SPICLM
t
SPICLKM
t
SPICHM
t
HDSM
t
SPITDM
t
HDSPIDM
LSB
VALID
LSB
MSB
MSB
VALID
t
HSPIDM
t
DDSPIDM
MOSI
(OUTPUT)
MISO
(INPUT)
t
SSPIDM
CPHASE=1
CPHASE=0
t
SDSCIM
t
SSPIDM
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