參數(shù)資料
型號: ADSP-21364SBBCZENG
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號處理
英文描述: SHARC Processor
中文描述: 16-BIT, 55.55 MHz, OTHER DSP, PBGA136
封裝: LEAD FREE, MO-205AE, MBGA-136
文件頁數(shù): 21/52頁
文件大小: 853K
代理商: ADSP-21364SBBCZENG
ADSP-21364
Preliminary Technical Data
Rev. PrB
|
Page 21 of 52
|
September 2004
Core Timer
The following timing specification applies to FLAG3 when it is
configured as the core timer (CTIMER).
Timer PWM_OUT Cycle Timing
The following timing specification applies to Timer0, Timer1,
and Timer2 in PWM_OUT (pulse width modulation) mode.
Timer signals are routed to the DAI_P20–1 pins through the
SRU. Therefore, the timing specifications provided below are
valid at the DAI_P20–1 pins.
Table 14. Core Timer
Parameter
Switching Characteristic
t
WCTIM
Min
Max
Unit
CTIMER Pulse Width
4 × t
PCLK
– 1
ns
Figure 11. Core Timer
FLAG3
(CTIMER)
t
WCTIM
Table 15. Timer PWM_OUT Timing
Parameter
Switching Characteristic
t
PWMO
Min
Max
Unit
Timer Pulse Width Output
2 t
PCLK
– 1
2(2
31
– 1) t
PCLK
ns
Figure 12. Timer PWM_OUT Timing
DAI_P20-1
(TIMER2-0)
t
PWMO
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