參數(shù)資料
型號： ADSP-21161NKCAZ100
廠商： Analog Devices Inc
文件頁數(shù)： 14/60頁
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 32BIT 225MBGA
產(chǎn)品培訓模塊： SHARC Processor Overview
標準包裝： 1
系列： SHARC®
類型： 浮點
接口： 主機接口，連接端口，串行端口
時鐘速率： 100MHz
非易失內(nèi)存： 外部
芯片上RAM： 128kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.80V
工作溫度： 0°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 225-BGA，CSPBGA
供應(yīng)商設(shè)備封裝： 225-CSPBGA（17x17）
包裝： 托盤
其它名稱： ADSP21161NKCAZ100
Rev. C
|
Page 21 of 60
|
January 2013
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
The number of output pins that switch during each cycle
(O)
The maximum frequency at which they can switch (f)
Their load capacitance (C)
Their voltage swing (VDD)
and is calculated by:
The load capacitance should include the processor package
capacitance (CIN). The switching frequency includes driving the
load high and then back low. At a maximum rate of 1/tCK,
address and data pins can drive high and low, while writing to a
SDRAM memory.
Example: Estimate PEXT with the following assumptions:
A system with one bank of external memory (32 bit)
Two 1M
16 SDRAM chips are used, each with a load of
10 pF (ignoring trace capacitance)
External Data Memory writes can occur every cycle at a
rate of 1/tCK with 50% of the pins switching
The bus cycle time is 55 MHz
The external SDRAM clock rate is 110 MHz
Ignoring SDRAM refresh cycles
Addresses are incremental and on the same page
The PEXT equation is calculated for each class of pins that can
drive, as shown in Table 9.
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:
Where:
PEXT is from Table 9.
PINT is IDDINT × 1.8 V, using the calculation IDDINT listed in Power
PPLL is AIDD × 1.8 V, using the value for AIDD listed in the Electri-
cal Characteristics on Page 18.
Note that the conditions causing a worst-case PEXT are different
from those causing a worst-case PINT. Maximum PINT cannot
occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching
simultaneously.
Table 8. Operation Types Versus Input Current
Operation
Peak Activity1 (IDDINPEAK)High Activity
DDINHIGH)Low Activity
DDINLOW)
Instruction Type
Multifunction
Single Function
Instruction Fetch
Cache
Internal Memory
Core Memory Access
2 per tCK cycle (DM64 and PM64)
1 per tCK cycle (DM64)
None
Internal Memory DMA
1 per 2 tCCLK cycles
N/A
External Memory DMA
1 per external port cycle (
32)
1 per external port cycle (
32)
N/A
Data bit pattern for core
memory access and DMA
Worst case
Random
N/A
1 The state of the PEYEN bit (SIMD versus SISD mode) does not influence these calculations.
2 These assume a 2:1 core clock ratio. For more information on ratios and clocks (t
CK and tCCLK), see the timing ratio definitions on Page 19.
P
EXT
OC
V
DD
2
f
=
P
TOTAL
P
EXT
P
INT
P
PLL
++
=
Table 9. External Power Calculations—110 MHz Instruction Rate
Pin Type
Number of Pins
% Switching
C
f
VDD
2
= PEXT
Address
11
20
24.7 pF
55 MHz
10.9 V
= 0.033 W
MSx
4
0
24.7 pF
N/A
10.9 V
= 0.000 W
SDWE
1
0
24.7 pF
N/A
10.9 V
= 0.000 W
Data
32
50
14.7 pF
55 MHz
10.9 V
= 0.141 W
SDCLK0
1
100
24.7 pF
110 MHz
10.9 V
= 0.030 W
PEXT = 0.204 W
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