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參數(shù)資料
| 型號： | ADSP-2109LKP-55 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Low Cost DSP Microcomputers |
| 中文描述： | 24-BIT, 13.824 MHz, OTHER DSP, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 5/36頁 |
| 文件大?。?/td> | 333K |
| 代理商： | ADSP-2109LKP-55 |
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ADSP-2104/ADSP-2109
REV. 0
–5–
T he interrupt control register, ICNT L, allows the external
interrupts to be set as either edge- or level-sensitive. Depending
on bit 4 in ICNT L, interrupt service routines can either be
nested (with higher priority interrupts taking precedence) or be
processed sequentially (with only one interrupt service active at
a time).
T he interrupt force and clear register, IFC, is a write-only register
that contains a force bit and a clear bit for each interrupt.
When responding to an interrupt, the AST AT , MST AT , and
IMASK status registers are pushed onto the status stack and
the PC counter is loaded with the appropriate vector address.
T he status stack is seven levels deep to allow interrupt nesting.
T he stack is automatically popped when a return from the
interrupt instruction is executed.
Pin Definitions
T able II shows pin definitions for the ADSP-2104/ADSP-2109
processors. Any inputs not used must be tied to V
DD
.
SY ST E M INT E RFACE
Figure 3 shows a typical system for the ADSP-2104/ADSP-2109,
with two serial I/O devices, a boot EPROM, and optional external
program and data memory. A total of 14.25K words of data
memory and 14.5K words of program memory is addressable.
Programmable wait-state generation allows the processors to
easily interface to slow external memories.
T he ADSP-2104/ADSP-2109 also provides either: one external
interrupt (
IRQ2
) and two serial ports (SPORT 0, SPORT 1),
or
three external interrupts (
IRQ2
,
IRQ1
,
IRQ0
) and one serial
port (SPORT 0).
Clock Signals
T he ADSP-2104/ADSP-2109’s CLK IN input may be driven by
a crystal or by a T T L-compatible external clock signal. T he
CLK IN input may not be halted or changed in frequency during
operation, nor operated below the specified low frequency limit.
If an external clock is used, it should be a T T L-compatible
signal running at the instruction rate. T he signal should be
connected to the processor’s CLK IN input; in this case, the
X T AL input must be left unconnected.
Because the processor includes an on-chip oscillator circuit, an
external crystal may also be used. T he crystal should be con-
nected across the CLK IN and X T AL pins, with two capacitors
connected as shown in Figure 2. A parallel-resonant, fundamen-
tal frequency, microprocessor-grade crystal should be used.
T able II. ADSP-2104/ADSP-2109 Pin Definitions
Pin
Name(s)
# of
Pins
Input /
Output
Function
Address
Data
1
14
24
O
I/O
Address outputs for program, data and boot memory.
Data I/O pins for program and data memories. Input only for
boot memory, with two MSBs used for boot memory addresses.
Unused data lines may be left floating.
Processor Reset Input
External Interrupt Request #2
External Bus Request Input
External Bus Grant Output
External Program Memory Select
External Data Memory Select
Boot Memory Select
External Memory Read Enable
External Memory Write Enable
Memory Map Select Input
External Clock or Quartz Crystal Input
Processor Clock Output
Power Supply Pins
Ground Pins
Serial Port 0 Pins
(TFS0, RFS0, DT0, DR0, SCLK0)
Serial Port 1 Pins
(TFS1, RFS1, DT1, DR1, SCLK1)
RESET
IRQ2
BR
2
BG
PMS
DMS
BMS
RD
WR
MMAP
CLK IN, X T AL
CLK OUT
V
DD
GND
SPORT 0
SPORT 1
or
Interrupts & Flags:
IRQ0
(RFS1)
IRQ1
(TFS1)
FI
(DR1)
FO
(DT1)
1
1
1
1
1
1
1
1
1
1
2
1
I
I
I
O
O
O
O
O
O
I
I
O
5
5
I/O
I/O
1
1
1
1
I
I
I
O
External Interrupt Request #0
External Interrupt Request #1
Flag Input Pin
Flag Output Pin
NOT ES
1
Unused data bus lines may be left floating.
2
BR
must be tied high (to V
DD
) if not used.
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