- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374032 > ADSP-21062LKS-160 (ANALOG DEVICES INC) ADSP-2106x SHARC DSP Microcomputer Family PDF資料下載
參數(shù)資料
| 型號： | ADSP-21062LKS-160 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | ADSP-2106x SHARC DSP Microcomputer Family |
| 中文描述： | 48-BIT, 40 MHz, OTHER DSP, PQFP240 |
| 封裝： | MS-029GA, MQFP-240 |
| 文件頁數(shù)： | 10/48頁 |
| 文件大?。?/td> | 370K |
| 代理商： | ADSP-21062LKS-160 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁
–10–
ADSP-21062/ADSP-21062L
REV. C
Pin
Type
Function
TFSx
I/O
Transmit Frame Sync
(Serial Ports 0, 1).
RFSx
I/O
Receive Frame Sync
(Serial Ports 0, 1).
LxDAT
3-0
I/O
Link Port Data
(Link Ports 0–5). Each LxDAT pin has a 50 k
internal pull-down resistor that is
enabled or disabled by the LPDRD bit of the LCOM register.
LxCLK
I/O
Link Port Clock
(Link Ports 0–5). Each LxCLK pin has a 50 k
internal pull-down resistor that is
enabled or disabled by the LPDRD bit of the LCOM register.
LxACK
I/O
Link Port Acknowledge
(Link Ports 0–5). Each LxACK pin has a 50 k
internal pull-down resistor
that is enabled or disabled by the LPDRD bit of the LCOM register.
EBOOT
I
EPROM Boot Select
. When EBOOT is high, the ADSP-21062 is configured for booting from an 8-
bit EPROM. When EBOOT is low, the LBOOT and
BMS
inputs determine booting mode. See table
below. This signal is a system configuration selection that should be hardwired.
LBOOT
I
Link Boot
. When LBOOT is high, the ADSP-21062 is configured for link port booting. When
LBOOT is low, the ADSP-21062 is configured for host processor booting or no booting. See table
below. This signal is a system configuration selection that should be hardwired.
BMS
I/O/T*
Boot Memory Select
.
Output
: Used as chip select for boot EPROM devices (when EBOOT= 1,
LBOOT = 0). In a multiprocessor system,
BMS
is output by the bus master.
Input:
When low, indi-
cates that no booting will occur and that ADSP-21062 will begin executing instructions from external
memory. See table below. This input is a system configuration selection that should be hardwired.
*Three-statable only in EPROM boot mode (when
BMS
is an output).
EBOOT
LBOOT
BMS
Booting Mode
1
0
0
0
0
1
0
0
1
0
1
1
Output
1 (Input)
1 (Input)
0 (Input)
0 (Input)
x (Input)
EPROM (Connect
BMS
to EPROM chip select.)
Host Processor
Link Port
No Booting. Processor executes from external memory.
Reserved
Reserved
CLKIN
I
Clock In
. External clock input to the ADSP-21062. The instruction cycle rate is equal to CLKIN.
CLKIN may not be halted, changed, or operated below the minimum specified frequency.
RESET
I/A
Processor Reset
. Resets the ADSP-21062 to a known state and begins program execution at the
program memory location specified by the hardware reset vector address. This input must be asserted
(low) at power-up.
TCK
I
Test Clock (JTAG)
. Provides an asynchronous clock for JTAG boundary scan.
TMS
I/S
Test Mode Select (JTAG)
. Used to control the test state machine. TMS has a 20 k
internal pull-up
resistor.
TDI
I/S
Test Data Input (JTAG)
. Provides serial data for the boundary scan logic. TDI has a 20 k
internal
pull-up resistor.
TDO
O
Test Data Output (JTAG)
. Serial scan output of the boundary scan path.
TRST
I/A
Test Reset (JTAG)
. Resets the test state machine.
TRST
must be asserted (pulsed low) after power-
up or held low for proper operation of the ADSP-21062.
TRST
has a 20 k
internal pull-up resistor.
EMU
O
Emulation Status
. Must be connected to the ADSP-21062 EZ-ICE
target board connector
only
.
ICSA
O
Reserved
, leave unconnected.
VDD
P
Power Supply
; nominally +5.0 V dc for 5 V devices or +3.3 V dc for 3.3 V devices. (30 pins)
GND
G
Power Supply Return
. (30 pins)
NC
Do Not Connect
. Reserved pins which must be left open and unconnected.
相關PDF資料 |
PDF描述 |
|---|---|
| ADSP-21062LCS-160 | ADSP-2106x SHARC DSP Microcomputer Family |
| ADSP-21062LAB-160 | ADSP-2106x SHARC DSP Microcomputer Family |
| ADSP-21062KB-160 | ADSP-2106x SHARC DSP Microcomputer Family |
| ADSP-21062 | ADSP-2106x SHARC DSP Microcomputer Family |
| ADSP-21062L | Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-21062LKSZ-133 | 功能描述:IC DSP CONTROLLER 32BIT 240MQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21062LKSZ-160 | 功能描述:IC DSP CONTROLLER 2MBIT 240MQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21065 | 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer |
| ADSP-21065L | 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer |
| ADSP-21065LCCA-240 | 功能描述:IC DSP CTLR 32BIT 196CSPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
發(fā)布緊急采購，3分鐘左右您將得到回復。