參數(shù)資料
型號(hào): ADSP-21062L
廠商: Analog Devices, Inc.
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection
中文描述: 無電容,NMOS管,150mA的低壓差穩(wěn)壓器的反向電流保護(hù)
文件頁數(shù): 41/48頁
文件大?。?/td> 370K
代理商: ADSP-21062L
ADSP-21062/ADSP-21062L
–41–
REV. C
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
DECAY
using the equation given above. Choose
V
to be the difference between the ADSP-21062’s output voltage
and the input threshold for the device requiring the hold time. A
typical
V will be 0.4 V. C
L
is the total bus capacitance (per
data line), and I
L
is the total leakage or three-state current (per
data line). The hold time will be t
DECAY
plus the minimum
disable time (i.e., t
DATRWH
for the write cycle).
REFERENCE
SIGNAL
t
DIS
OUTPUT STARTS
DRIVING
V
OH (MEASURED)
V
V
OL (MEASURED)
+ V
t
DECAY
t
MEASURED
V
OH (MEASURED)
V
OL (MEASURED)
2.0V
1.0V
V
OH (MEASURED)
V
OL (MEASURED)
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE TO BE
APPROXIMATELY 1.5V
OUTPUT STOPS
DRIVING
t
ENA
Figure 25. Output Enable/Disable
+1.5V
50pF
TO
OUTPUT
PIN
I
OL
I
OH
Figure 26. Equivalent Device Loading for AC Measure-
ments (Includes All Fixtures)
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
50 pF on all pins (see Figure 26). The delay and hold specifica-
tions given should be derated by a factor of 1.5 ns/50 pF for
loads other than the nominal value of 50 pF. Figures 29–30,
33–34 show how output rise time varies with capacitance. Fig-
ures 31, 35 show graphically how output delays and holds vary
with load capacitance. (Note that this graph or derating does
not apply to output disable delays; see the previous section
Output Disable Time
under Test Conditions.) The graphs of
Figures 29, 30 and 31 may not be linear outside the ranges
shown.
INPUT OR
OUTPUT
1.5V
1.5V
Figure 27. Voltage Reference Levels for AC Measure-
ments (Except Output Enable/Disable)
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