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參數(shù)資料
| 型號： | ADSP-21062KB-160 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | ADSP-2106x SHARC DSP Microcomputer Family |
| 中文描述： | 48-BIT, 40 MHz, OTHER DSP, PBGA225 |
| 封裝： | PLASTIC, MS-034AAJ-2, BGA-225 |
| 文件頁數(shù)： | 9/48頁 |
| 文件大?。?/td> | 370K |
| 代理商： | ADSP-21062KB-160 |
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ADSP-21062/ADSP-21062L
–9–
REV. C
Pin
Type
Function
SBTS
I/S
Suspend Bus Three-State
. External devices can assert
SBTS
(low) to place the external bus address,
data, selects and strobes in a high impedance state for the following cycle. If the ADSP-21062
attempts to access external memory while
SBTS
is asserted, the processor will halt and the memory
access will not be completed until
SBTS
is deasserted.
SBTS
should only be used to recover from host
processor/ADSP-21062 deadlock, or used with a DRAM controller.
IRQ
2-0
I/A
Interrupt Request Lines
. May be either edge-triggered or level-sensitive.
FLAG
3-0
I/O/A
Flag Pins
. Each is configured via control bits as either an input or output. As an input, they can be
tested as a condition. As an output, they can be used to signal external peripherals.
TIMEXP
O
Timer Expired
. Asserted for four cycles when the timer is enabled and TCOUNT decrements to
zero.
HBR
I/A
Host Bus Request
. This pin must be asserted by a host processor to request control of the
ADSP-21062’s external bus. When
HBR
is asserted in a multiprocessing system, the ADSP-21062
that is bus master will relinquish the bus and assert
HBG
. To relinquish the bus, the ADSP-21062
places the address, data, select and strobe lines in a high impedance state.
HBR
has priority over all
ADSP-21062 bus requests (
BR
6-1
) in a multiprocessing system.
HBG
I/O
Host Bus Grant
. Acknowledges an
HBR
bus request, indicating that the host processor may take
control of the external bus.
HBG
is asserted (held low) by the ADSP-21062 until
HBR
is released. In
a multiprocessing system,
HBG
is output by the ADSP-21062 bus master and is monitored by all others.
CS
I/A
Chip Select
. Asserted by host processor to select the ADSP-21062.
REDY (O/D) O
Host Bus Acknowledge
. The ADSP-21062 deasserts REDY (low) to add wait states to an asynchro-
nous access of its internal memory or IOP registers by a host. This pin is an open drain output (O/D)
by default; it can be programmed in the ADREDY bit of the SYSCON register to be active drive
(A/D). REDY will only be output if the
CS
and
HBR
inputs are asserted.
DMAR1
I/A
DMA Request 1
(DMA Channel 7).
DMAR2
I/A
DMA Request 2
(DMA Channel 8).
DMAG1
O/T
DMA Grant 1
(DMA Channel 7).
DMAG2
O/T
DMA Grant 2
(DMA Channel 8).
BR
6-1
I/O/S
Multiprocessing Bus Requests
. Used by multiprocessing ADSP-21062s to arbitrate for bus master-
ship. An ADSP-21062 only drives its own
BR
x line (corresponding to the value of its ID
2-0
inputs) and
monitors all others. In a multiprocessor system with less than six ADSP-21062s, the unused
BR
x pins
should be pulled high; the processor’s own
BR
x line must not be pulled high or low because it is an
output.
ID
2-0
I
Multiprocessing ID
. Determines which multiprocessing bus request (
BR1
–
BR6
) is used by ADSP-
21062. ID = 001 corresponds to
BR1
, ID = 010 corresponds to
BR2
, etc. ID = 000 in single-processor
systems. These lines are a system configuration selection which should be hardwired or changed at
reset only.
RPBA
I/S
Rotating Priority Bus Arbitration Select
. When RPBA is high, rotating priority for multiprocessor
bus arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system con-
figuration selection which must be set to the same value on every ADSP-21062. If the value of RPBA is
changed during system operation, it must be changed in the same CLKIN cycle on every ADSP-21062.
CPA
(O/D)
I/O
Core Priority Access
. Asserting its
CPA
pin allows the core processor of an ADSP-21062 bus slave
to interrupt background DMA transfers and gain access to the external bus.
CPA
is an open drain
output that is connected to all ADSP-21062s in the system. The
CPA
pin has an internal 5 k
pull-up
resistor. If core access priority is not required in a system, the
CPA
pin should be left unconnected.
DTx
O
Data Transmit
(Serial Ports 0, 1). Each DT pin has a 50 k
internal pull-up resistor.
Data Receive
(Serial Ports 0, 1). Each DR pin has a 50 k
internal pull-up resistor.
DRx
I
TCLKx
I/O
Transmit Clock
(Serial Ports 0, 1). Each TCLK pin has a 50 k
internal pull-up resistor.
RCLKx
I/O
Receive Clock
(Serial Ports 0, 1). Each RCLK pin has a 50 k
internal pull-up resistor.
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| ADSP-21062 | ADSP-2106x SHARC DSP Microcomputer Family |
| ADSP-21062L | Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection |
| ADSP-21062LKB-160 | ADSP-2106x SHARC DSP Microcomputer Family |
| ADSP-21065LCCA-240 | DSP Microcomputer |
| ADSP-21065LKS-240 | DSP Microcomputer |
相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ADSP-21062KBZ-160 | 功能描述:IC DSP CONTROLLER 32BIT 225BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
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| ADSP21062KS160 | 制造商:AD 功能描述:New |
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