參數(shù)資料
型號(hào): ADSP-21061LKB-176
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號(hào)處理
英文描述: ADSP-2106x SHARC DSP Microcomputer Family
中文描述: 48-BIT, 44 MHz, OTHER DSP, PBGA225
封裝: PLASTIC, BGA-225
文件頁(yè)數(shù): 35/47頁(yè)
文件大?。?/td> 367K
代理商: ADSP-21061LKB-176
ADSP-21061/ADSP-21061L
–35–
REV. B
DT
t
DDTTI
t
DDTIN
DRIVE
EDGE
DRIVE
EDGE
TCLK / RCLK
TCLK (INT)
TFS ("LATE", INT)
DT
t
DDTTE
t
DDTEN
DRIVE
EDGE
DRIVE
EDGE
TCLK / RCLK
TCLK (EXT)
TFS ("LATE" EXT)
t
SDRI
RCLK
RFS
DR
DRIVE
EDGE
SAMPLE
EDGE
t
HDRI
t
SFSI
t
HFSI
t
DFSE
t
HOFSE
t
SCLKIW
DATA RECEIVE– INTERNAL CLOCK
t
SDRE
DATA RECEIVE– EXTERNAL CLOCK
RCLK
RFS
DR
DRIVE
EDGE
SAMPLE
EDGE
t
HDRE
t
SFSE
t
HFSE
t
DFSE
t
SCLKW
t
HOFSE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
t
DDTI
t
HDTI
TCLK
TFS
DT
DRIVE
EDGE
SAMPLE
EDGE
t
SFSI
t
HFSI
t
SCLKIW
t
DFSI
t
HOFSI
DATA TRANSMIT– INTERNAL CLOCK
t
DDTE
t
HDTE
TCLK
TFS
DT
DRIVE
EDGE
SAMPLE
EDGE
t
SFSE
t
HFSE
t
DFSE
t
SCLKW
t
HOFSE
DATA TRANSMIT– EXTERNAL CLOCK
CLKIN
SPORT ENABLE AND
THREE-STATE
LATENCY
IS TWO CYCLES
t
DPTR
t
DCLK
LOW TO HIGH ONLY
TCLK (INT)
RCLK (INT)
TCLK, RCLK
TFS, RFS, DT
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
SPORT DISABLE DELAY
FROM INSTRUCTION
Figure 21. Serial Ports
相關(guān)PDF資料
PDF描述
ADSP-21061LKS-160 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21061LKS-176 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21062CS-160 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21062KS-133 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21062KS-160 ADSP-2106x SHARC DSP Microcomputer Family
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