參數(shù)資料
型號(hào)： ADSP-21061LKB-160
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 26/52頁(yè)
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 32BIT 225BGA
產(chǎn)品培訓(xùn)模塊： SHARC Processor Overview
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點(diǎn)
接口： 同步串行端口（SSP）
時(shí)鐘速率： 40MHz
非易失內(nèi)存： 外部
芯片上RAM： 128kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： 0°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 225-BBGA
供應(yīng)商設(shè)備封裝： 225-PBGA
包裝： 托盤
Rev. D | Page 32 of 52 | May 2013
Asynchronous Read/Write—Host to ADSP-21061
Use these specifications for asynchronous host processor
accesses of an ADSP-21061, after the host has asserted CS and
HBR (low). After HBG is returned by the ADSP-21061, the host
can drive the RD and WR pins to access the ADSP-21061’s
internal memory or IOP registers. HBR and HBG are assumed
low for this timing.
Table 17. Read Cycle
5 V and 3.3 V
Unit
Parameter
Min
Max
Timing Requirements
tSADRDL
Address Setup/CS Low Before RD Low1
0ns
tHADRDH
Address Hold/CS Hold Low After RD
0ns
tWRWH
RD/WR High Width
6
ns
tDRDHRDY
RD High Delay After REDY (O/D) Disable
0
ns
tDRDHRDY
RD High Delay After REDY (A/D) Disable
0
ns
Switching Characteristics
tSDATRDY
Data Valid Before REDY Disable from Low
2
ns
tDRDYRDL
REDY (O/D) or (A/D) Low Delay After RD Low2
10
ns
tRDYPRD
REDY (O/D) or (A/D) Low Pulsewidth for Read
45 + DT
ns
tHDARWH
Data Disable After RD High
2
8
ns
1 Not required if RD and address are valid t
HBGRCSV after HBG goes low. For first access after HBR asserted, ADDR31-0 must be a non-MMS value 1/2 tCLK before RD or WR goes
low or by tHBGRCSV after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Processor Control of the
ADSP-21061” section in the ADSP-2106x SHARC User’s Manual.
2 For the ADSP-21061L (3.3 V), this specification is 13.5 ns max.
Table 18. Write Cycle
5 V and 3.3 V
Unit
Parameter
Min
Max
Timing Requirements
tSCSWRL
CS Low Setup Before WR Low
0
ns
tHCSWRH
CS Low Hold After WR High
0
ns
tSADWRH
Address Setup Before WR High
5
ns
tHADWRH
Address Hold After WR High
2
ns
tWWRL
WR Low Width
8
ns
tWRWH
RD/WR High Width
6
ns
tDWRHRDY
WR High Delay After REDY (O/D) or (A/D) Disable
0
ns
tSDATWH
Data Setup Before WR High
50 MHz, tCK = 20 ns1
3
2.5
ns
tHDATWH
Data Hold After WR High
1
ns
Switching Characteristics
tDRDYWRL
REDY (O/D) or (A/D) Low Delay After WR/CS Low2
11
ns
tRDYPWR
REDY (O/D) or (A/D) Low Pulsewidth for Write
15
ns
tSRDYCK
REDY (O/D) or (A/D) Disable to CLKIN
1 + 7DT/16
8 + 7DT/16 ns
1 This specification applies to the ADSP-21061KS-200 (5 V, 50 MHz) operating at t
CK < 25 ns. For all other devices, use the preceding timing specification of the same name.
2 For the ADSP-21061L (3.3 V), this specification is 13.5 ns max.
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