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參數(shù)資料
| 型號： | ADSP-21061L |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | ADSP-2106x SHARC DSP Microcomputer Family |
| 中文描述： | 的ADSP - 2106x SHARC處理器DSP的微機家庭 |
| 文件頁數(shù)： | 23/47頁 |
| 文件大?。?/td> | 367K |
| 代理商： | ADSP-21061L |
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ADSP-21061/ADSP-21061L
–23–
REV. B
Synchronous Read/Write—Bus Master
Use these specifications for interfacing to external memory
systems that require CLKIN—relative timing or for accessing a
slave ADSP-21061 (in multiprocessor memory space). These
synchronous switching characteristics are also valid during
asynchronous memory reads and writes (see Memory Read—
Bus Master and Memory Write—Bus Master).
When accessing a slave ADSP-2106x, these switching character-
istics must meet the slave’s timing requirements for synchronous
read/writes (see Synchronous Read/Write—Bus Slave). The
slave ADSP-21061 must also meet these (bus master) timing
requirements for data and acknowledge setup and hold times.
ADSP-21061 (5 V)
Min
ADSP-21061L (3.3 V)
Min
Parameter
Max
Max
Unit
Timing Requirements:
t
SSDATI
t
SSDATI
(50 MHz) Data Setup before CLKIN,
t
CK
= 20 ns
1
t
HSDATI
Data Hold after CLKIN
t
DAAK
ACK Delay after Address,
MS
x,
SW
,
BMS
2, 3
t
SACKC
ACK Setup before CLKIN
2
t
HACK
ACK Hold after CLKIN
Switching Characteristics:
t
DADRO
Address,
MS
x,
BMS
,
SW
Delay
after CLKIN
2
t
HADRO
Address,
MS
x,
BMS
,
SW
Hold
after CLKIN
t
DPGC
PAGE Delay after CLKIN
t
DRDO
RD
High Delay after CLKIN
t
DWRO
WR
High Delay after CLKIN
t
DWRO
(50 MHz)
WR
High Delay after CLKIN,
t
CK
= 20 ns
1
t
DRWL
RD
/
WR
Low Delay after CLKIN
t
SDDATO
Data Delay after CLKIN
t
DATTR
Data Disable after CLKIN
4
t
DADCCK
ADRCLK Delay after CLKIN
t
ADRCK
ADRCLK Period
t
ADRCKH
ADRCLK Width High
t
ADRCKL
ADRCLK Width Low
Data Setup before CLKIN
2 + DT/8
2 + DT/8
ns
1.5 + DT/8
3.5 – DT/8
ns
ns
3.5 – DT/8
15 + 7 DT/8 + W
15 + 7 DT/8 + W
ns
ns
ns
6.5 + DT/4
–1 – DT/4
6.5 + DT/4
–1 – DT/4
6.5 – DT/8
6.5 – DT/8
ns
–1 – DT/8
9 + DT/8
–1.5 – DT/8
–2.5 – 3DT/16
–1 – DT/8
9 + DT/8
–1.5 – DT/8
–2.5 – 3DT/16
ns
ns
ns
ns
16 + DT/8
4 – DT/8
4 – 3DT/16
16 + DT/8
4 – DT/8
4 – 3DT/16
–1.5 – 3DT/16
8 + DT/4
4 – 3DT/16
12 + DT/4
19 + 5DT/16
7 – DT/8
10 + DT/8
ns
ns
ns
ns
ns
ns
ns
ns
8 + DT/4
12 + DT/4
19 + 5DT/16
7 – DT/8
10 + DT/8
0 – DT/8
4 + DT/8
t
CK
(t
CK
/2 – 2)
(t
CK
/2 – 2)
0 – DT/8
4 + DT/8
t
CK
(t
CK
/2 – 2)
(t
CK
/2 – 2)
W = (number of Wait states specified in WAIT register)
×
t
CK
.
NOTES
1
This specification applies to the ADSP-21061KS-200 (5 V, 50 MHz) operating at t
CK
< 25 ns. For all other devices, use the preceding timing specification of the
same name.
2
ACK Delay/Setup: User must meet t
DAAK
or t
DSAK
or synchronous specification t
SACKC
for deassertion of ACK (Low), all three specifications must be met for assertion
of ACK (High).
3
Data Hold: User must meet t
or t
HDRH
or synchronous specification t
HDATI
. See
System Hold Time Calculation
under Test Conditions for the calculation of hold
times given capacitive and dc loads.
4
See
System Hold Time Calculation
under Test Conditions for calculation of hold times given capacitive and dc loads.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADSP-21061LAS-160 | ADSP-2106x SHARC DSP Microcomputer Family |
| ADSP-21061LAS-176 | ADSP-2106x SHARC DSP Microcomputer Family |
| ADSP-21061KS-160 | ADSP-2106x SHARC DSP Microcomputer Family |
| ADSP-21061KS-200 | ADSP-2106x SHARC DSP Microcomputer Family |
| ADSP-21061LKB-160 | ADSP-2106x SHARC DSP Microcomputer Family |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-21061LAS-160 | 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2106x SHARC DSP Microcomputer Family |
| ADSP-21061LAS-176 | 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit 44MHz 44MIPS 240-Pin MQFP Tray 制造商:Analog Devices 功能描述:IC MICROCOMPUTER DSP |
| ADSP-21061LASZ-176 | 功能描述:IC DSP CONTROLLER 32BIT 240MQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-21061LKB-160 | 功能描述:IC DSP CONTROLLER 32BIT 225BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21061LKB-176 | 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer Family |
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