參數(shù)資料
型號(hào): ADSP-21060LKS-133
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號(hào)處理
英文描述: ADSP-2106x SHARC DSP Microcomputer Family
中文描述: 48-BIT, 33.33 MHz, OTHER DSP, PQFP240
封裝: MS-029GA, MQFP-240
文件頁(yè)數(shù): 32/47頁(yè)
文件大小: 366K
代理商: ADSP-21060LKS-133
–32–
ADSP-21060/ADSP-21060L
REV. D
Link Ports: 1
×
CLK Speed Operation
ADSP-21060
Min
ADSP-21060L
Min
Parameter
Max
Max
Units
Receive
Timing Requirements:
t
SLDCL
t
HLDCL
t
LCLKIW
t
LCLKRWL
t
LCLKRWH
Data Setup before LCLK Low
Data Hold after LCLK Low
LCLK Period (1
×
Operation)
LCLK Width Low
LCLK Width High
3.5
3
t
CK
6
5
3
3
t
CK
6
5
ns
ns
ns
ns
ns
Switching Characteristics:
t
DLAHC
t
DLALC
t
ENDLK
t
TDLK
LACK High Delay after CLKIN High
LACK Low Delay after LCLK High
1
LACK Enable from CLKIN
LACK Disable from CLKIN
18 + DT/2
–3
5 + DT/2
28.5 + DT/2
13
18 + DT/2
–3
5 + DT/2
28.5 + DT/2
13
ns
ns
ns
ns
20 + DT/2
20 + DT/2
Transmit
Timing Requirements:
t
SLACH
t
HLACH
LACK Setup before LCLK High
LACK Hold after LCLK High
18
–7
20
–7
ns
ns
Switching Characteristics:
t
DLCLK
t
DLDCH
t
HLDCH
t
LCLKTWL
t
LCLKTWH
t
DLACLK
t
ENDLK
t
TDLK
LCLK Delay after CLKIN (1
×
operation)
Data Delay after LCLK High
Data Hold after LCLK High
LCLK Width Low
LCLK Width High
LCLK Low Delay after LACK High
LDAT, LCLK Enable after CLKIN
LDAT, LCLK Disable after CLKIN
15.5
3
16.5
2.5
ns
ns
ns
ns
ns
ns
ns
ns
–3
(t
CK
/2) – 2
(t
CK
/2) – 2
(t
CK
/2) + 8.5
5 + DT/2
–3
(t
CK
/2) – 1
(t
CK
/2) – 1.25
(t
CK
/2) + 8.0
5 + DT/2
(t
CK
/2) + 2
(t
CK
/2) + 2
(3
×
t
CK
/2) + 17
(t
CK
/2) + 1.25
(t
CK
/2) + 1.0
(3
×
t
CK
/2) + 17.5
20 + DT/2
20 + DT/2
Link Port Service Request Interrupts: 1
×
and
2
×
Speed Operations
Timing Requirements:
t
SLCK
LACK/LCLK Setup before CLKIN Low
2
t
HLCK
LACK/LCLK Hold after CLKIN Low
2
10
2
10
2
ns
ns
NOTES
1
LACK will go low with t
DLALC
relative to rising edge of LCLK after first nibble is received. LACK will not go low if the receiver’s link buffer is not about to fill.
2
Only required for interrupt recognition in the current cycle.
相關(guān)PDF資料
PDF描述
ADSP-21060LKS-160 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21061KS-133 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21061 ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21061L ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21061LAS-160 ADSP-2106x SHARC DSP Microcomputer Family
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-21060LKS-160 功能描述:IC DSP CONTROLLER 32BIT 240MQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP(數(shù)字式信號(hào)處理器) 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI,以太網(wǎng),RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA(20x20) 包裝:托盤
ADSP-21060LKSZ-133 功能描述:IC DSP CONTROLLER 32BIT 240-MQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP(數(shù)字式信號(hào)處理器) 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI,以太網(wǎng),RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA(20x20) 包裝:托盤
ADSP-21060LKSZ-160 功能描述:IC DSP CONTROLLER 32BIT 240MQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP(數(shù)字式信號(hào)處理器) 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI,以太網(wǎng),RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA(20x20) 包裝:托盤
ADSP-21061 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21061KS 制造商:Analog Devices 功能描述: