參數(shù)資料
型號(hào): ADSP-2105KP-80
廠商: ANALOG DEVICES INC
元件分類(lèi): 數(shù)字信號(hào)處理
英文描述: ADSP-2100 Family DSP Microcomputers
中文描述: 24-BIT, 20 MHz, OTHER DSP, PQCC68
封裝: PLASTIC, LCC-68
文件頁(yè)數(shù): 30/64頁(yè)
文件大?。?/td> 666K
代理商: ADSP-2105KP-80
ADSP-21xx
–30–
REV. B
TIMNGPARAMETERS (ADSP-2101/2105/2111/2115/2161/2163)
CLOCK SIGNALS & RE SE T
Frequency
Dependency
Min
13 MHz
Min
13.824 MHz
Min
16.67 MHz
Min
20 MHz
Min
25 MHz
Min
Parameter
Max
Max
Max
Max
Max
Max
Unit
Timing Requirement:
t
CK
CLK IN Period
t
CK L
CLK IN Width Low
t
CK H
CLK IN Width High
t
RSP
RESET
Width Low
Switching Characteristic:
t
CPL
CLK OUT Width Low
t
CPH
CLK OUT Width High
t
CK OH
CLK IN High to CLK OUT
High
76.9
20
20
384.5
150
72.3
20
20
361.5
150
60
20
20
300
150
50
20
20
250
150
40
15
15
200
150
ns
ns
ns
ns
20
20
5t
CK1
28.5
28.5
0
26.2
26.2
0
20
20
0
15
15
0
10
10
0
0.5t
CK
– 10
0.5t
CK
– 10
ns
ns
ns
20
20
20
20
15
NOT ES
1
Applies after powerup sequence is complete. Internal phase lock loop requires no more than 2000 CLK IN cycles, assuming stable CLK IN (not including crystal
oscillator startup time).
Figure 29. Clock Signals
CLKIN
CLKOUT
t
CKH
t
CK
t
CKL
t
CKOH
t
CPH
t
CPL
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