參數(shù)資料
型號(hào)： ADSP-2104
廠商： Analog Devices, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： low cost DSP microcomputers
中文描述： 低成本DSP單片機(jī)
文件頁數(shù)： 7/36頁
文件大?。?/td> 333K
代理商： ADSP-2104
ADSP-2104/ADSP-2109
REV. 0
–7–
Program Memory Maps
Program memory can be mapped in two ways, depending on
the state of the MMAP pin. Figure 4 shows the ADSP-2104
program memory maps. Figure 5 shows the program memory
maps for the ADSP-2109.
INTERNAL RAM
512 WORDS
LOADED FROM
EXTERNAL
BOOT MEMORY
EXTERNAL
14K
0x01FF
0x3FFF
0x0000
EXTERNAL
14K
0x39FF
0x3A00
0x3FFF
0x0000
MMAP=0
MMAP=1
No Booting
0x37FF
0x3800
0x07FF
0x0800
INTERNAL RAM
512 WORDS
1.5K
RESERVED
1.5K
RESERVED
Figure 4. ADSP-2104 Program Memory Maps
4K
INTERNAL
ROM
12K
EXTERNAL
0x3FFF
0x0000
2K
EXTERNAL
0x3FFF
0x0000
MMAP=0
MMAP=1
0x37FF
0x3800
2K
INTERNAL
ROM
2K
INTERNAL
ROM
10K
EXTERNAL
0x07FF
0x0800
0x0FF0
0x0FFF
0x1000
0x0FF0
0x0FFF
0x1000
RESERVED
RESERVED
Figure 5. ADSP-2109 Program Memory Maps
ADSP-2104
When MMAP = 0, on-chip program memory RAM occupies
512 words beginning at address 0x0000. Off-chip program
memory uses the remaining 14K words beginning at address
0x0800. In this configuration–when MMAP = 0–the boot
loading sequence (described below in “Boot Memory Inter-
face”) is automatically initiated when
RESET
is released.
When MMAP = 1, 14K words of off-chip program memory
begin at address 0x0000 and on-chip program memory RAM is
located in the 512 words between addresses 0x3800–0x39FF. In
this configuration, program memory is not booted although it
can be written to and read under program control.
Data Memory Interface
T he data memory address bus (DMA) is 14 bits wide. T he
bidirectional external data bus is 24 bits wide, with the upper 16
bits used for data memory data (DMD) transfers.
T he data memory select (
DMS
) signal indicates access to data
memory and can be used as a chip select signal. T he write (
WR
)
signal indicates a write operation and can be used as a write
strobe. T he read (
RD
) signal indicates a read operation and can
be used as a read strobe or output enable signal.
T he ADSP-2104/ADSP-2109 processors support memory-
mapped I/O, with the peripherals memory-mapped into the data
memory address space and accessed by the processor in the
same manner as data memory.
Data Memory Map
ADSP-2104
On-chip data memory RAM resides in the 256 words beginning
at address 0x3800, also shown in Figure 6. Data memory
locations from 0x3900 to the end of data memory at 0x3FFF
are reserved. Control and status registers for the system, timer,
wait-state configuration, and serial port operations are located in
this region of memory.
0x3900
0x0400
0x0000
1K EXTERNAL
DWAIT0
1K EXTERNAL
DWAIT1
10K EXTERNAL
DWAIT2
1K EXTERNAL
DWAIT3
0x0800
0x3000
256 WORDS
0x3C00
0x3FFF
1K EXTERNAL
DWAIT4
0x3400
0x3800
MEMORY-MAPPED
CONTROL REGISTERS
& RESERVED
EXTERNAL
RAM
INTERNAL
RAM
Figure 6. Data Memory Map
T he remaining 14K of data memory is located off-chip. T his
external data memory is divided into five zones, each associated
with its own wait-state generator. T his allows slower peripherals
to be memory-mapped into data memory for which wait states
are specified. By mapping peripherals into different zones, you
can accommodate peripherals with different wait-state require-
ments. All zones default to seven wait states after
RESET
.
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參數(shù)描述
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