參數(shù)資料
型號(hào)： ADS8472IRGZT
英文描述： 16-BIT, 1-MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE, REFERENCE
中文描述： 16位，1 MSPS的，偽雙極，全差分輸入，微采樣模擬到數(shù)字轉(zhuǎn)換并行接口，參考
文件頁(yè)數(shù)： 24/30頁(yè)
文件大?。?/td> 814K
代理商： ADS8472IRGZT
www.ti.com
Reading Data
RESET
On power-up, internal POWER-ON RESET circuitry generates the reset required for the device. The first three
conversions after power-up are used to load factory trimming data for a specific device to assure high accuracy
of the converter. The results of the first three conversions are invalid and should be discarded.
ADS8472
SLAS514–DECEMBER 2006
PRINCIPLES OF OPERATION (continued)
Conversions are initiated by bringing the CONVST pin low for a minimum of 20 ns (after the 20 ns minimum
requirement has been met, the CONVST pin can be brought high), while CS is low. The ADS8472 switches from
the sample to the hold mode on the falling edge of the CONVST command. A clean and low jitter falling edge of
this signal is important to the performance of the converter. The BUSY output is brought high immediately
following CONVST going low. BUSY stays high throughout the conversion process and returns low when the
conversion has ended.
Sampling starts with the falling edge of the BUSY signal when CS is tied low or starts with the falling edge of CS
when BUSY is low.
Both RD and CS can be high during and before a conversion with one exception (CS must be low when
CONVST goes low to initiate a conversion). Both the RD and CS pins are brought low in order to enable the
parallel output bus with the conversion.
The ADS8472 outputs full parallel data in straight binary format as shown in
Table 1
. The parallel output is
active when CS and RD are both low. There is a minimal quiet zone requirement around the falling edge of
CONVST. This is 50 ns prior to the falling edge of CONVST and 40 ns after the falling edge. No data read
should attempted within this zone. Any other combination of CS and RD sets the parallel output to 3-state. BYTE
is used for multiword read operations. BYTE is used whenever lower bits on the bus are output on the higher
byte of the bus. Refer to
Table 1
for ideal output codes.
Table 1. Ideal Input Voltages and Output Codes
DESCRIPTION
Full scale range
Least significant bit (LSB)
+Full scale
Midscale
Midscale – 1 LSB
Zero
ANALOG VALUE
+V
ref
2
×
(+V
ref
)/65536
(+V
ref
) – 1 LSB
0 V
0 V – 1 LSB
–V
ref
DIGITAL OUTPUT STRAIGHT BINARY
BINARY CODE
0111 1111 1111 1111
0000 0000 0000 0000
1111 1111 1111 1111
1000 0000 0000 0000
HEX CODE
1FFF
0000
3FFF
2000
The output data is a full 16-bit word (D15–D0) on DB15–DB0 pins (MSB–LSB) if BYTE is low.
The result may also be read on an 8-bit bus for convenience. This is done by using only pins DB15–DB8. In this
case two reads are necessary: the first as before, leaving BYTE low and reading the 8 most significant bits on
pins DB15–DB8, then bringing BYTE high. When BYTE is high, the low bits (D7–D0) appear on pins
DB15–DB8.
All of these multiword read operations can be performed with multiple active RD (toggling) or with RD held low
for simplicity. This is referred to as the AUTO READ operation.
Table 2. Conversion Data Read Out
DATA READ OUT
BYTE
PINS
PINS
DB7–DB0
All One's
D7–D0
DB15–DB8
D7–D0
D15–D8
High
Low
The device can also be reset through the use of the combination fo CS and CONVST. Since the BUSY signal is
held at high during the conversion, either one of these conditions triggers an internal self-clear reset to the
converter.
24
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