
13
ADS820
DYNAMIC PERFORMANCE TESTING
The ADS820 is a high performance converter and careful
attention to test techniques is necessary to achieve accurate
results. Highly accurate phase-locked signal sources allow
high resolution FFT measurements to be made without using
data windowing functions. A low jitter signal generator such
as the HP8644A for the test signal, phase-locked with a low
jitter HP8022A pulse generator for the A/D clock, gives
excellent results. Low pass filtering (or bandpass filtering)
of test signals is absolutely necessary to test the low distor-
tion of the ADS820. Using a signal amplitude slightly lower
than full scale will allow a small amount of “headroom” so
that noise or DC offset voltage will not overrange the A/D
and cause clipping on signal peaks.
DYNAMIC PERFORMANCE DEFINITIONS
1. Signal-to-Noise-and-Distortion Ratio (SINAD):
Sinewave Signal Power
Noise + Harmonic Power (first 15 harmonics)
10 log
2. Signal-to-Noise Ratio (SNR):
Sinewave Signal Power
Noise Power
10 log
3. Intermodulation Distortion (IMD):
Highest IMD Product Power (to 5th-order)
Sinewave Signal Power
10 log
IMD is referenced to the larger of the test signals f
1
or f
2
.
Five “bins” either side of peak are used for calculation of
fundamental and harmonic power. The “0” frequency bin
(DC) is not included in these calculations as it is of little
importance in dynamic signal processing applications.
EXTERNAL REFERENCES AND ADJUSTMENT OF
FULL SCALE RANGE
The internal reference buffers are limited to approximately
1mA of output current. As a result, these internal +1.25V
and +3.25V references may be overridden by external refer-
ences that have at least 18mA (at room temperature) of
output drive capability. In this instance, the common-mode
voltage will be set halfway between the two references. This
feature can be used to adjust the gain error, improve gain
drift, or to change the full scale input range of the ADS820.
Changing the full scale range to a lower value has the benefit
of easing the swing requirements of external input amplifi-
ers. The external references can vary as long as the value of
the external top reference (REFT
EXT
) is less than or equal to
+3.4V and the value of the external bottom reference
(REFB
EXT
) is greater than or equal to +1.1V and the differ-
ence between the external references are greater than or
equal to 800mV.
For the differential configuration, the full scale input range
will be set to the external reference values that are selected.
For the single-ended mode, the input range is 2(REFT
EXT
–
REFB
EXT
), with the common-mode being centered at
(REFT
EXT
+ REFB
EXT
)/2. Refer to the typical performance
curves for expected performance vs full scale input range.
The circuit in Figure 9 works completely on a single +5V
supply. As a reference element, it uses the micro-power
reference REF1004-2.5, which is set to a quiescent current
of 0.1mA. Amplifier A
2
is configured as a follower to buffer
the +1.25V generated from the resistor divider. To provide
the necessary current drive, a pull-down resistor, R
P
is
added.
Amplifier A
1
is configured as an adjustable gain stage, with
a range of approximately 1 to 1.32. The pull-up resistor
again relieves the op amp from providing the full current
drive. The value of the pull-up/down resistors is not critical
and can be varied to optimize power consumption. The need
for pull-up/down resistors depends only on the drive capa-
bility of the selected drive amplifiers and thus can be
omitted.
PC BOARD LAYOUT AND BYPASSING
A well-designed, clean PC board layout will assure proper
operation and clean spectral response. Proper grounding and
bypassing, short lead lengths, and the use of ground planes
are particularly important for high frequency circuits. Mul-
tilayer PC boards are recommended for best performance
but if carefully designed, a two-sided PC board with large,
heavy ground planes can give excellent results. It is recom-
mended that the analog and digital ground pins of the
ADS820 be connected directly to the analog ground plane.
In our experience, this gives the most consistent results. The
A/D power supply commons should be tied together at the
analog ground plane. Power supplies should be bypassed
with 0.1
μ
F ceramic capacitors as close to the pin as possible.