參數(shù)資料
型號(hào)： ADS7953SRHBT
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： ADC
英文描述： 16-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PQCC32
封裝： GREEN, PLASTIC, PQFP-32
文件頁(yè)數(shù)： 17/63頁(yè)
文件大?。?/td> 1734K
代理商： ADS7953SRHBT
th
2
1
2
3
4
5
6
14
15
16
CS
SCLK
SDO
SDI
DO-
15
DO-
14
DO-
13
DO-
12
DO-11
MSB
DO-10
MSB-1
DO-0
LSB
DO-1
LSB+1
DO-2
LSB+2
DI-15
DI-14
DI-12
DI-11
DI-10
DI-2
DI-1
DI-0
a
tsu 1
td
1
td 2
th 1
tsu2
td 3
tw 1
tq
1 /tthroughput (singleframe)
DI-13
1
2
3
4
5
6
14
15
16
CS\
SCLK
SDO
SDI
DO-
15
DO-
14
DO-
13
DO-
12
DO-11
MSB
DO-10
MSB-1
DO-0
-
DO-1
-
DO-2
LSB
DI-15
DI-14
DI-13
DI-12
DI-11
DI-10
DI-2
DI-1
DI-0
a
tsu1
td1
td2
th1
tsu2
th2
td3
tw1
tq
1/t throughput (single frame)
CS
1
2
3
4
5
6
12
13
16
CS\
SCLK
SDO
SDI
DO-
15
DO-
14
DO-
13
DO-
12
DO-11
MSB
DO-10
MSB-1
DO-0
-
DO-3
-
DO-4
LSB
DI-15
DI-14
DI-13
DI-12
DI-11
DI-10
DI-4
DI-3
DI-0
a
tsu1
td1
td2
th1
tsu2
th2
td3
tw1
tq
1/t throughput (single frame)
CS
SLAS605A – JUNE 2008 – REVISED JANUARY 2010
www.ti.com
Figure 46. Serial Interface Timing Diagram for 12-Bit Devices ( ADS7950/51/52/53)
Figure 47. Serial Interface Timing Diagram for 10-Bit Devices (ADS7954/55/56/57)
Figure 48. Serial Interface Timing Diagram for 8-Bit Devices (ADS7958/59/60/61)
The falling edge of CS clocks out DO-15 (first bit of the four bit channel address), and remaining address bits are
clocked out on every falling edge of SCLK until the third falling edge. The conversion result MSB is clocked out
on the 4th SCLK falling edge and LSB on the 15th/13th/11th falling edge respectively for 12/10/8-bit devices. On
the 16th falling edge of SCLK, SDO goes to the 3-state condition. The conversion ends on the 16th falling edge
of SCLK.
The device reads a sixteen bit word on the SDI pin while it outputs the data on the SDO pin. SDI data is latched
on every rising edge of SCLK starting with the 1st clock as shown in Figure 46, Figure 47, and Figure 48.
CS can be asserted (pulled high) only after 16 clocks have elapsed.
24
Copyright 2008–2010, Texas Instruments Incorporated
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