
SLAS605A – JUNE 2008 – REVISED JANUARY 2010
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REVISION HISTORY
Changes from Original (June 2008) to Revision A
Page
Added QFN information to Features .....................................................................................................................................
1Added QFN information to Description .................................................................................................................................
1Added QFN information to 12-bit ordering information .........................................................................................................
3Added QFN information to 10-bit ordering information .........................................................................................................
3Added QFN information to 8-bit ordering information ...........................................................................................................
4Changed thermal impedance for DBT package in absolute maximum ratings ....................................................................
4Changed thermal impedance for RHB package in absolute maximum ratings ....................................................................
4Changed thermal impedance for RGE package in absolute maximum ratings ....................................................................
4Added Vref = 2.5 V ± 0.1 V to ELECTRICAL CHARACTERISTICS, ADS7950/51/52/53 ..................................................... 5 Added while 2Vref
≤ +VA to full-scale input span range 2 test conditions ...........................................................................
5Added while 2Vref
≤ +VA to full-scale input span range 2 test conditions ...........................................................................
5Added Total unadjusted error (TUE) specification ................................................................................................................
5Changed reference voltage at REFP min and max values ..................................................................................................
6Added Vref = 2.5 V ± 0.1 V to ELECTRICAL CHARACTERISTICS, ADS7950/51/52/53 ..................................................... 6 Added Note to ELECTRICAL CHARACTERISTICS, ADS7950/51/52/53 ............................................................................
6Added Vref = 2.5 V ± 0.1 V to ELECTRICAL CHARACTERISTICS, ADS7954/55/56/57 test conditions ............................. 6 Added while 2Vref
≤ +VA to full-scale input span range 2 test conditions ...........................................................................
6Added while 2Vref
≤ +VA to full-scale input span range 2 test conditions ...........................................................................
6Added Vref = 2.5 V ± 0.1 V to ELECTRICAL CHARACTERISTICS, ADS7954/55/56/57 test conditions ............................. 7 Changed Vref reference voltage at REFP min value from 2.49 V to 2.0 V ........................................................................... 7 Changed Vref reference voltage at REFP max value from 2.51 V to 3.0 V .......................................................................... 7 Added Vref = 2.5 V ± 0.1 V to ELECTRICAL CHARACTERISTICS, ADS7954/55/56/57 test conditions ............................. 8 Added Vref = 2.5 V ± 0.1 V to ELECTRICAL CHARACTERISTICS, ADS7958/59/60/61 test conditions ............................. 8 Added while 2Vref
≤ +VA to full-scale input span range 2 test conditions ...........................................................................
8Added while 2Vref
≤ +VA to full-scale input span range 2 test conditions ...........................................................................
8Changed Vref reference voltage at REFP min value from 2.49 V to 2.0 V ........................................................................... 9 Changed Vref reference voltage at REFP max value from 2.51 V to 3.0 V .......................................................................... 9 Added Vref = 2.5 V ± 0.1 V to ELECTRICAL CHARACTERISTICS, ADS7958/59/60/61 test conditions ............................. 9 Changed tsu1 values from max to min ................................................................................................................................. 10 Changed tsu2 values from max to min ................................................................................................................................. 10 Changed VEE to AGND and VCC to +VA on 38-pin TSSOP pinout .................................................................................
11Added QFN pinout ..............................................................................................................................................................
11Added QFN pinout ..............................................................................................................................................................
12Added QFN pinout ..............................................................................................................................................................
12Added QFN pinout ..............................................................................................................................................................
12Added terminal functions for QFN packages ......................................................................................................................
14Changed ADS7950/4/8 QFN package MXO pin from 7 to 3 ..............................................................................................
14Added TOTAL UNADJUSTED ERROR (TUE Max) graph .................................................................................................
21Added TOTAL UNADJUSTED ERROR (TUE Min) graph ..................................................................................................
21Changed GPIO pins description .........................................................................................................................................
23Added device powerdown through GPIO in the case of the TSSOP packaged devices ...................................................
25Added note to
Table 1 ........................................................................................................................................................
29Added note to
Table 1 ........................................................................................................................................................
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