- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375265 > ADS7861E CMOS 4-Bit-by-16-Word FIFO Register 16-PDIP -55 to 125 PDF資料下載
參數(shù)資料
| 型號： | ADS7861E |
| 英文描述： | CMOS 4-Bit-by-16-Word FIFO Register 16-PDIP -55 to 125 |
| 中文描述： | 雙通道，為500kHz，12位，2通道，同步采樣模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 11/15頁 |
| 文件大?。?/td> | 226K |
| 代理商： | ADS7861E |
11
ADS7861
FIGURE 8. Conversion Mode.
HIGH within this window, it is then uncertain as to when the
ADS7861 will initiate conversion (see Figure 8 for a more
detailed description). Sixteen clock cycles are required to
perform a single conversion. Immediately following
CONVST switching to HIGH, the ADS7861 will switch
from the sample mode to the hold mode asynchronous to the
external clock. The BUSY output pin will then go HIGH and
remain HIGH for the duration of the conversion cycle. On
the falling edge of the first cycle of the external clock, the
ADS7861 will latch in the address for the next conversion
cycle depending on the status of the A0 pin (HIGH =
Channel 1, LOW = Channel 0). The address must be selected
15ns prior to the falling edge of cycle one of the external
clock and must remain ‘held’ for 15ns following the clock
edge. For maximum throughput time, the CONVST and RD
pins should be tied together. CS must be brought LOW to
enable the two serial outputs. Data will be valid on the rising
edge of all 16 clock cycles per conversion. The first bit of
data will be a status flag for either Channel 0 or 1, the second
bit will be a second status flag for either Channel A or B.
The subsequent data will be MSB-first through the LSB,
followed by two zeros (see Table II and Figures 9 and 10).
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
COMMENTS
t
CONV
t
ACQ
t
CKP
t
CKL
t
CKH
t
F
t
R
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
Conversion Time
Acquisition Time
Clock Period
Clock LOW
Clock HIGH
DOUT Fall Time
DOUT Rise Time
CONVST HIGH
Address Setup Time
Address Hold Time
RD Setup Time
RD to CS Hold Time
CONVST LOW
RD LOW
CS to Data Valid
CLOCK to Data Valid Delay
Data Valid After CLOCK
(1)
1.75
0.25
125
40
40
μ
s
μ
s
ns
ns
ns
ns
ns
ns
ns
When T
CKP
= 125ns
When T
CKP
= 125ns
5000
25
30
15
15
15
15
15
20
20
Address latched on falling edge of CLK cycle ‘2’
ns
ns
ns
ns
ns
ns
ns
Before falling edge of CLOCK
After falling edge of CLOCK
25
30
1
Maximum delay following rising edge of CLOCK
Time data is valid after second rising edge of CLOCK
NOTE: (1) ‘n – 1’ data will remain valid 1ns after rising edge of next CLOCK cycle.
TIMING SPECIFICATIONS
CLOCK CYCLE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SERIAL DATA
CH0 OR CH1 CHA OR CHB
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
TABLE II. Serial Data Output Format.
NOTE: All CONVST commands which occur more than 10ns before the rising edge of cycle ‘1’ of the external clock
(Region ‘A’) will initiate a conversion on the rising edge of cycle ‘1’. All CONVST commands which occur 5ns after
the rising edge of cycle ‘1’ or 10ns before the rising edge of cycle 2 (Region ‘B’) will initiate a conversion on the
rising edge of cycle ‘2’. All CONVST commands which occur 5ns after the rising edge of cycle ‘2’ (Region ‘C’) will
initiate a conversion on the rising edge of the next clock period. The CONVST pin should never be switched from
LOW to HIGH in the region 10ns prior to the rising edge of the CLOCK and 5ns after the rising edge (gray areas). If
CONVST is toggled in this gray area, the conversion could begin on either the same rising edge of the CLOCK or
the following edge.
CLOCK
CONVST
Cycle 1
Cycle 2
t
CKP
125ns
10ns
5ns
10ns
5ns
A
B
C
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADS7861EB | CMOS 4-Bit-by-16-Word FIFO Register 16-PDIP -55 to 125 |
| ADS801 | 12-Bit, 25MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS801E | 12-Bit, 25MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS801U | REC3-SRW_DRW/H* Series - Econoline Regulated DC-DC Converters; Input Voltage (Vdc): 12V; Output Voltage (Vdc): 12V; Power: 3W; 2kV, 4kVDC & 6kVDC Isolation; Industry Standard 3W DIP24 Package; Feedback Regulated Output; Continuous Short Circuit Protection; Wide Input 2:1 & 4:1; Medical Approvals (4kV/6kV Versions); EN and UL Certificates; 3 Pinout Options, 3 Case Styles; Control Pin Option; Efficiency to 86% |
| ADS802 | 12-Bit, 10MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS7861E | 制造商:BURR-BROWN 功能描述:12BIT ADC DUAL SMD 7861 SSOP24 制造商:Texas Instruments 功能描述:Analog-Digital Converter IC Number of Bi |
| ADS7861E/2K5 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual 500kHz 2+2 Ch Simltns Smplng ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7861E/2K5G4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual 500kHz 2+2 Ch Simltns Smplng ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7861EB | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual 500kHz 2+2 Ch Simltns Smplng ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7861EB | 制造商:Texas Instruments 功能描述:Analog/Digital Converter IC Number of Bi |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。