參數(shù)資料
型號: ADS62P45IRGC25
廠商: Texas Instruments
文件頁數(shù): 59/78頁
文件大?。?/td> 0K
描述: IC ADC 14B SER/PAR 125M 64VQFN
標(biāo)準(zhǔn)包裝: 25
位數(shù): 14
采樣率(每秒): 125M
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 64-VQFN 裸露焊盤(9x9)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個差分,單極
t Time s
8120
8140
8160
8180
8200
8220
8240
8260
0
2
4
6
8
10
12
14
Code
LSB
G084
Device With
Offset Cancelled
Device With
Initial Offset
Offset Loop
Enabled Here
SLAS561C
– JULY 2007 – REVISED FEBRUARY 2012
It is also possible to freeze the offset correction using the serial interface (
<OFFSET LOOP FREEZE>). Once
frozen, the offset estimation becomes inactive and the last estimated value is used for correction every clock
cycle. Note that the offset correction is disabled by default after reset.
Figure 101 shows the time response of the offset correction algorithm, after it is enabled.
Figure 101. Time Response of Offset Correction
Gain Correction
ADS62P4X has ability to make fine corrections to the ADC channel gain. The corrections can be done in steps of
0.05 dB, up to a maximum of 0.5 dB, using the register bits ( GAIN CORRECTION). Only positive corrections are
supported and the same correction applies to both the channels.
Table 23. Gain Correction Values
<GAIN CORRECTION>
AMOUNT OF CORRECTION,
D3-D2-D1-D0
dB
0000
0
0001
+0.05
0010
+0.1
0011
+0.15
0100
+0.20
0101
+0.25
0110
+0.30
0111
+0.35
1000
+0.40
1001
+0.45
1010
+0.5
Other combinations
Unused
62
Copyright
2007–2012, Texas Instruments Incorporated
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