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參數(shù)資料
| 型號： | ADS1244IDGSRG4 |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 2/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC LP CONVERT 24BIT 10-MSOP |
| 產(chǎn)品培訓模塊： | Data Converter Basics |
| 視頻文件： | Nuts and Bolts of the Delta-Sigma Converter |
| 標準包裝： | 2,500 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 15 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 270µW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，單極；1 個差分，雙極 |
| 配用： | 296-18359-ND - EVALUATION MODULE FOR ADS1244 |
ADS1244
10
SBAS273
www.ti.com
POWER-UP
Self-calibration is performed at power-up to minimize offset and
gain errors. In order for the self-calibration at power-up to work
properly, make sure that both AVDD and DVDD increase
monotonically and are settled by t1, as shown in Figure 11.
SCLK must be held LOW during this time. Once calibration is
complete, DRDY/DOUT will go LOW indicating data is ready
for retrieval. The time required before the first data is ready (t6)
depends on how fast AVDD and DVDD ramp to their final value
(t1). For most ramp rates, t1 + t2 ≈ 350ms (fCLK = 2.4576MHz).
If the system environment is not stable during power-up (the
temperature is varying or the supply voltages are moving
around), it is recommended that a self-calibration be issued
after everything is stable.
DATA FORMAT
The ADS1244 outputs 24 bits of data in Binary Two’s
Complement format. The Least Significant Bit (LSB) has a
weight of (2VREF)/(223 – 1). A positive full-scale input pro-
FIGURE 11. Power-Up Timing.
AVDD and DVDD
DRDY/DOUT
SCLK
t
1
t
2
Data ready after power-up calibration.
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
t1(1)
AVDD and DVDD settling time.
100
ms
t2(1)
Wait time for calibration and first data conversion.
316
ms
NOTE: (1) Values given for fCLK = 2.4576MHz. For different CLK frequencies, scale proportional
to CLK period.
duces an output code of 7FFFFFH and the negative full-scale
input produces an output code of 800000H. The output clips
at these codes for signals exceeding full-scale. Table I
summarizes the ideal output codes for different input signals.
INPUT SIGNAL VIN (AINP – AINN)
IDEAL OUTPUT CODE(1)
≥ +2V
REF
7FFFFFH
+
2
21
23
VREF
000001H
0
000000H
2
21
23
VREF
FFFFFFH
≤
2
21
23
VREF
800000H
NOTE: (1) Excludes effects of noise, INL, offset, and gain errors.
TABLE I. Ideal Output Code versus Input Signal.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS1244IDGST | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-Bit Delta-Sigma 15SPS w/50-60Hz rej RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1244IDGSTG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-Bit Delta-Sigma 15SPS w/50-60Hz rej RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1245 | 制造商:BB 制造商全稱:BB 功能描述:Low-Power, 24-Bit Analog-to-Digital Converter |
| ADS1245IDGSR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-bit Low-Power w/Hi-Z Input Buffer RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1245IDGSRG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-bit Low-Power w/Hi-Z Input Buffer RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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