- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374031 > ADS1000A1IDBVT (Analog Devices, Inc.) LOW POWER, 12-Bit ANALOG-TO-DIGITAL CONVERTER with I2C⑩ INTERFACE PDF資料下載
參數(shù)資料
| 型號： | ADS1000A1IDBVT |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | LOW POWER, 12-Bit ANALOG-TO-DIGITAL CONVERTER with I2C⑩ INTERFACE |
| 中文描述： | 低功耗，12位模擬數(shù)字轉(zhuǎn)換接口的I2C⑩ |
| 文件頁數(shù)： | 6/17頁 |
| 文件大?。?/td> | 240K |
| 代理商： | ADS1000A1IDBVT |
www.ti.com
ADS1000
SBAS357–SEPTEMBER 2006
An I
2
C bus consists of two lines, SDA and SCL. SDA
carries data; SCL provides the clock. All data is
transmitted across the I
2
C bus in groups of eight bits.
To send a bit on the I
2
C bus, the SDA line is driven
to the bit level while SCL is low (a Low on SDA
indicates the bit is '0'; a High indicates the bit is '1').
Once the SDA line has settled, the SCL line is
brought high, then low. This pulse on SCL clocks the
SDA bit into the receiver shift register.
The I
2
C bus is bidirectional: the SDA line is used
both for transmitting and receiving data. When a
master reads from a slave, the slave drives the data
line; when a master sends to a slave, the master
drives the data line. The master always drives the
clock line. The ADS1000 never drives SCL, because
it cannot act as a master. On the ADS1000, SCL is
an input only.
10-bit addresses; see the I
2
C specification for
details.) The master sends an address in the
address byte, together with a bit that indicates
whether it wishes to read from or write to the slave
device.
Every byte transmitted on the I
2
C bus, whether it be
address
or
data,
is
acknowledge
bit. When a master has finished
sending a byte, eight data bits, to a slave, it stops
driving SDA and waits for the slave to acknowledge
the byte. The slave acknowledges the byte by pulling
SDA low. The master then sends a clock pulse to
clock the acknowledge bit. Similarly, when a master
has finished reading a byte, it pulls SDA low to
acknowledge to the slave that it has finished reading
the byte. It then sends a clock pulse to clock the bit.
(Remember that the master always drives the clock
line.)
acknowledged
with
an
Most of the time the bus is idle, no communication
takes
place,
and
both
communication takes place, the bus is active. Only
master devices can start a communication. They do
this by causing a start condition on the bus.
Normally, the data line is only allowed to change
state while the clock line is low. If the data line
changes state while the clock line is high, it is either
a
start
condition or its counterpart, a
stop
condition.
A start condition is when the clock line is high and
the data line goes from high to low. A stop condition
is when the clock line is high and the data line goes
from low to high.
lines
are
high.
When
A
not-acknowledge
is performed by simply leaving
SDA high during an acknowledge cycle. If a device is
not present on the bus, and the master attempts to
address it, it will receive a not-acknowledge because
no device is present at that address to pull the line
low.
When a master has finished communicating with a
slave, it may issue a stop condition. When a stop
condition is issued, the bus becomes idle again. A
master may also issue another start condition. When
a start condition is issued while the bus is active, it is
called a
repeated start condition
.
A timing diagram for an ADS1000 I
2
C transaction is
shown in
Figure 6
.
Table 1
gives the parameters for
this diagram.
After the master issues a start condition, it sends a
byte that indicates with which slave device it wants to
communicate. This byte is called the
address byte
.
Each device on an I
2
C bus has a unique 7-bit
address to which it responds. (Slaves can also have
6
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADS1000A1IDBVTG4 | LOW POWER, 12-Bit ANALOG-TO-DIGITAL CONVERTER with I2C⑩ INTERFACE |
| ADS1000 | LOW POWER, 12-Bit ANALOG-TO-DIGITAL CONVERTER with I2C⑩ INTERFACE |
| ADS1000A0IDBVR | LOW POWER, 12-Bit ANALOG-TO-DIGITAL CONVERTER with I2C⑩ INTERFACE |
| ADS1000A0IDBVRG4 | LOW POWER, 12-Bit ANALOG-TO-DIGITAL CONVERTER with I2C⑩ INTERFACE |
| ADS1000A0IDBVT | LOW POWER, 12-Bit ANALOG-TO-DIGITAL CONVERTER with I2C⑩ INTERFACE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS1000A1IDBVT | 制造商:Texas Instruments 功能描述:A/D Converter (A-D) IC |
| ADS1000A1IDBVTG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit ADC with I2C Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1000A1QDBVRQ1 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Auto Cat Low Cost 12B ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1000AOIDBVT | 制造商:Texas Instruments 功能描述: |
| ADS1000-Q1 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:LOW-POWER 12-BIT ANALOG-TO-DIGITAL CONVERTER WITH I2Ca?￠ INTERFACE |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。