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參數(shù)資料
| 型號： | ADS-930 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 串行ADC |
| 英文描述： | 16-Bit, 500kHz Sampling A/D Converters |
| 中文描述： | 16位，500kHz的采樣A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 603K |
| 代理商： | ADS-930 |
ADS -930
4
DELAY
PIN
TRANSITION
MIN.
TYP.
MAX.
UNITS
Direct mode to FIFO enabled
23
–
10
20
ns
FIFO enabled to direct mode
23
–
10
20
ns
FIFO READ to output data valid
10
–
–
40
ns
FIFO READ to status update when changing
from <half full (1 word) to empty
10
–
–
28
ns
FIFO READ to status update when changing
from
≥
half full (8 words) to <half full (7 words)
10
–
–
110
ns
FIFO READ to status update when changing
from full (16 words) to
≥
half full (15 words)
10
–
–
190
ns
Falling edge of EOC to status update when writing
first word into empty FIFO
15
–
–
190
ns
Falling edge of EOC to status update when
changing FIFO from <half full (7 words) to
≥
half full (8 words)
15
–
–
110
ns
Falling edge of EOC to status update when filling
FIFO with 16th word
15
–
–
28
ns
Table 1. FIFO Delays
1
0
1
0
1
0
1
0
0
1
0
1
0
1
1
0
1
0
INTERNAL FIFO OPERATION
The ADS-930 contains an internal, user-initiated, 18-bit, 16-
word FIFO memory. Each word in the FIFO contains the 16
data bits as well as the MSB and OVERFLOW bits. Pins 23
(FIFO/DIR) and 10 (FIFO READ) control the FIFO's operation.
The FIFO's status can be monitored by reading pins 19
(FSTAT1) and 20 (FSTAT2).
When pin 23 (FIFO/DIR) has a logic "1" applied, the FIFO is
inserted into the digital data path. When pin 23 has a logic "0"
applied, the FIFO is transparent, and the output data goes
directly to the output three-state register (whose operation is
controlled by pin 9 (ENABLE)). Read and write commands to
the FIFO are ignored when the ADS-930 is operated in the
"direct" mode. It takes a maximum of 20ns to switch the FIFO
in or out of the ADS-930's operation.
FIFO WRITE and READ Modes
Once the FIFO has been enabled (pin 23 high), digital data is
automatically written to it, regardless of the status of FIFO
READ (pin 10). Assuming the FIFO is initially empty, it will
accept data (18-bit words) from the next 16 consecutive A/D
conversions. As a precaution, pin 10 (which controls the
FIFO's READ function) should not be low when data is first
written to an empty FIFO.
When the FIFO is initially empty, digital data from the first
conversion (the "oldest" data) appears at the output of the
FIFO immediately after the first conversion has been
completed and remains there until the FIFO is read.
If the output three-state register has been enabled (logic "0"
applied to pin 9), data from the first conversion will appear at
the output of the ADS-930. Attempting to write a 17th word
to a full FIFO will result in that data, and any subsequent
conversion data, being lost.
Once the FIFO is full (indicated by FSTAT1 and FSTAT2
both = "1"), it can be read by dropping the FIFO READ line
(pin 10) to a logic "0" and then applying a series of 15 rising
edges to the read line. Since the first data word is already
present at the FIFO output, the first read command (the first
rising edge applied to FIFO READ) will bring data from the
second conversion to the output. Each subsequent read
command/rising edge brings the next word to the output
lines.
If a read command is issued after the FIFO has been
emptied, the last word (the 16th conversion) will remain
present at the outputs.
FIFO Reset Feature
At any time, the FIFO can be reset to an empty state by
putting the ADS-930 into its "direct" mode (logic "0" applied
to pin 23, FIFO/DIR) and also applying a logic "0" to the
FIFO READ line (pin 10). The empty status of the FIFO will
be indicated by FSTAT1 going to a "0" and FSTAT2 going to
a "1". The status outputs will change 40ns after the control
signals have been applied.
FIFO Status, FSTAT1 and FSTAT2
The status of the data in the FIFO can be monitored by
reading the two status pins, FSTAT1 (pin 19) and FSTAT2
(pin 20).
CONTENTS
FSTAT1
FSTAT2
Empty (0 words)
0
1
<half full (
≤
7 words)
half-full or more (
≥
8 words)
Full (16 words)
0
1
1
0
0
1
it to be either connected to +5V or left open when a logic "1"
is required.
4. To enable the three-state outputs, connect ENABLE (pin 9)
to a logic "0" (low). To disable, connect pin 9 to a logic "1"
(high).
5. Applying a start convert pulse while a conversion is in
progress (EOC = logic "1") will initiate a new and probably
inaccurate conversion cycle.
6. Do not enable/disable or complement the output bits or
read from the FIFO during the conversion process (from the
falling edge of START CONVERT to the falling edge of
EOC).
TECHNICAL NOTES cont.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADS-930MC | 16-Bit, 500kHz Sampling A/D Converters |
| ADS-930MM | 16-Bit, 500kHz Sampling A/D Converters |
| ADS-EVAL3 | 16-Bit, 500kHz Sampling A/D Converters |
| ADS5444_07 | 13-BIT 250 MSPS ANALOG-TO-DIGITAL CONVERTER |
| ADS8383EVM | ADS8383EVM(ADS8383評估板) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS-930/883 | 制造商:Murata Power Solutions 功能描述:Single ADC Pipelined 500ksps 16-bit Parallel 40-Pin CTDIP |
| ADS930E | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8-Bit 30 MSPS SE/ Diff Input RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS930E | 制造商:Texas Instruments 功能描述:IC's |
| ADS930E/1K | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8-Bit 30 MSPS SE/ Diff Input RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS930E/1KG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8-Bit 30 MSPS SE/ Diff Input RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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