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參數(shù)資料
| 型號： | ADP3180JRU-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 6-Bit Programmable 2-, 3-, 4-Phase Synchronous Buck Controller |
| 中文描述： | SWITCHING CONTROLLER, 4000 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | MO-153-AE, TSSOP-28 |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 529K |
| 代理商： | ADP3180JRU-REEL7 |
ADP3180
–16–
COMP Pin Ramp
There is a ramp signal on the COMP pin due to the droop volt-
age and output voltage ramps. This ramp amplitude adds to the
internal ramp to produce the following overall ramp signal at the
PWM input.
V
V
(
1
n
C
D
×
n
f
R
RT
R
×
SW
X
O
=
×
×
)
×
1
2
(21)
For this example, the overall ramp signal is found to be 0.63 V.
Current Limit Set Point
To select the current limit set point, we need to find the resistor
value for
R
LIM
. The current limit threshold for the ADP3180 is set
with a 3 V source (
V
LIM
) across
R
LIM
with a gain of 10.4 mV/μA
(
A
LIM
).
R
LIM
can be found using the following:
R
A
V
I
R
LIM
LIM
LIM
LIM
O
=
×
×
(22)
For values of
R
LIM
greater than 500 k
W
, the current limit may be
lower than expected, so some adjustment of
R
LIM
may be needed.
Here,
I
LIM
is the average current limit for the output of the sup-
ply. For our example, choosing 120 A for
I
LIM
, we find
R
LIM
to be
200 k
W
, for which we chose 200 k
W
as the nearest 1% value.
The per phase current limit described earlier has its limit deter-
mined by the following:
I
V
V
V
A
R
I
PHLIM
COMP MAX
R
BIAS
D
DS MAX
R
×
)
)
2
(23)
For the ADP3180, the maximum COMP voltage (
V
COMP(MAX)
) is
3.3 V, the COMP pin bias voltage (
V
BIAS
) is 1.2 V, and the cur-
rent balancing amplifier gain (
A
D
) is 5. Using
V
R
of 0.63 V and
R
DS(MAX)
of 4.2 m
W
(low side ON resistance at 150°C), we find a
per phase limit of 66 A.
This limit can be adjusted by changing the ramp voltage
V
R
. But
make sure not to set the per phase limit lower than the average
per phase current (I
LIM
/n).
There is also a per phase initial duty cycle limit determined by:
D
D
V
V
V
MAX
COMP MAX
BIAS
RT
=
×
)
(24)
For this example, the maximum duty cycle is found to be 0.42.
Feedback Loop Compensation Design
Optimized compensation of the ADP3180 allows the best pos-
sible response of the regulator’s output to a load change. The
basis for determining the optimum compensation is to make the
regulator and output decoupling appear as an output imped-
ance that is entirely resistive over the widest possible frequency
range, including dc, and equal to the droop resistance (R
O
). With
the resistive output impedance, the output voltage will droop in
proportion with the load current at any load current slew rate;
this ensures the optimal positioning and allows the minimization
of the output decoupling.
With the multimode feedback structure of the ADP3180, one
needs to set the feedback compensation to make the converter’s
output impedance working in parallel with the output decoupling
meet this goal. There are several poles and zeros created by the
output inductor and decoupling capacitors (output filter) that
need to be compensated for.
A type-three compensator on the voltage feedback is adequate for
proper compensation of the output filter. The expressions given
in Equations 25–29 are intended to yield an optimal starting
point for the design; some adjustments may be necessary to
account for PCB and component parasitic effects (See the Tuning
Procedure for the ADP3180 section).
The first step is to compute the time constants for all of the poles
and zeros in the system:
R
n
R
A
R
R
V
V
L
n
R
D
×
×
3 6 56
V
n
C
V
600
R
m
m
m
V
V
nH
V
mF
E
O
D
DS
L
RT
VID
RT
X
O
2
VID
E
=
×
+
×
+
×
+
×
×
×
×
(
)
×
×
.
=
+ ×
5
+
×
+
×
1 3
.
(
)
×
×
×
2
1
3 1 3
4 2
.
1 6
.
0 63
1 5
.
1 0 375
.
0 63
.
1 5
.
.
.
m
V
m
=
37 9
.
(25)
T
C
R
R
L
R
R
R
R
mF
m
m
pH
m
m
m
m
s
A
X
O
X
O
O
X
=
×
(
)
+
×
=
×
(
)
+
×
=
'
'
.
.
.
.
.
.
.
.
6 56
1 3
0 6
375
1 3
1 3
0 6
1 0
4 79
μ
(26)
T
R
R
R
C
m
m
m
mF
s
B
X
O
X
=
+
(
)
×
=
+
(
)
×
=
'
.
.
.
.
.
1 0
0 6
1 3
6 56
1 97
μ
(27)
T
V
L
A
2
R
f
SW
V
R
V
nH
m
kHz
V
m
s
C
RT
D
DS
VID
E
=
×
×
×
×
=
×
×
×
×
=
0 63
.
600
5
2
4 2
267
1 5
.
37 9
6 2
.
.
.
μ
(28)
T
C
(
C
R
R
C
C
R
R
mF
m
F
m
m
mF
F
m
ns
D
X
Z
'
O
X
O
Z
O
=
×
×
×
)
+
×
=
×
×
×
(
)
+
×
=
2
2
6.
230
0 6
230
6 56
.
1 3
.
1 3
.
521
1 3
)
.
μ
μ
(29)
where, for the ADP3180,
R
' is the PCB resistance from the
bulk capacitors to the ceramics and where
R
DS
is the total low
side MOSFET ON resistance per phase. For this example,
A
D
is 5,
V
RT
equals 0.63 V,
R
' is approximately 0.6 m
W
(assuming
a 4-layer motherboard), and
L
X
is 375 pH for the eight Al-Poly
capacitors.
The compensation values can then be solved using the following:
C
n
R
T
R
R
m
C
s
m
k
pF
A
O
×
A
E
B
A
=
×
×
=
×
1 33
.
×
=
3 1 3
37 9
4 79
.
371
.
.
μ
(30)
REV. 0
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