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參數(shù)資料
| 型號(hào)： | ADNS-3060 |
| 英文描述： | High-performance Optical Mouse Sensor |
| 中文描述： | 高性能的光學(xué)鼠標(biāo)傳感器 |
| 文件頁數(shù)： | 14/38頁 |
| 文件大小： | 530K |
| 代理商： | ADNS-3060 |
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14
Synchronous Serial Port
The synchronous serial port is
used to set and read
parameters in the ADNS-3060,
and to read out the motion
information. The serial port is
also used to load SROM data
into the ADNS-3060.
The port is a four-wire, serial
port. The host micro-
controller always initiates
communication; the ADNS-
3060 never initiates data
transfers. The serial port
cannot be activated while the
chip is in power down mode
(NPD low) or reset (RESET
high). SCLK, MOSI, and NCS
may be driven directly by a
3.3V output from a micro-
controller, or they may be
placed in an open drain
configuration by enabling on-
chip pull-up current sources.
The open drain drive allows
the use of a 5V micro-
controller without any level
shifting components. The port
pins may be shared with other
SPI slave devices. When the
NCS pin is high, the inputs are
ignored and the output is tri-
stated.
The lines which comprise the
SPI port are:
SCLK: Clock input. It is always
generated by the master (the
micro- controller).
MOSI: Input data (Master Out/
Slave In).
MISO: Output data (Master In/
Slave Out).
NCS: Chip select input (active
low).
NCS needs to be low to
activate the serial port;
otherwise, MISO will be high-Z,
and MOSI & SCLK will be
ignored. NCS can also be used
to reset the serial port in case
of an error.
Figure 14. Idd vs. Frame Rate
Chip Select Operation
The serial port is activated
after NCS goes low. If NCS is
raised during a transaction,
the entire transaction is
aborted and the serial port
will be reset. This is true for
all transactions including
SROM download. After a
transaction is aborted, the
normal address-to-data or
transaction-to-transaction
delay is still required before
beginning the next transaction.
To improve communication
reliability, all serial
transactions should be framed
by NCS. In other words, the
port should not remain
enabled during periods of non-
use because ESD and EFT/B
events could be interpreted as
serial communication and put
the chip into an unknown
state. In addition, NCS must
be raised after each burst-
mode transaction is complete
to terminate burst-mode. The
port is not available for
further use until burst-mode is
terminated.
Average Supply Current vs Frame Rate
VDD=3.6V, Regulator Bypass Mode
72%
88%
100%
51%
55%
0%
20%
40%
60%
80%
100%
120%
0
2000
4000
6000
8000
Frame Rate (Hz)
R
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|---|---|
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