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參數(shù)資料
| 型號： | ADN8810-EVAL |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit High Output Current Source |
| 中文描述： | 12位高輸出電流源 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大小： | 232K |
| 代理商： | ADN8810-EVAL |
ADN8810
TIMING CHARACTERISTICS
1, 2
Table 2. Timing Characteristics
Parameter
f
CLK
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
NOTES
1
Guaranteed by design. Not production tested.
2
Sample tested during initial release and after any redesign or process change that may affect these parameters. All input signals are measured with tr = tf = 5 ns (10%
to 90% of DVDD) and timed from a voltage level of (V
IL
+ V
IH
)/2.
Rev. 0 | Page 5 of 16
Description
SCLK Frequency
SCLK Cycle Time
SCLK Width High
SCLK Width Low
CS Low to SCLK High Setup
CS High to SCLK High Setup
SCLK High to CS Low Hold
SCLK High to CS High Hold
Data Setup
Data Hold
CS High Pulsewidth
RESET Pulsewidth
CS High to RESET Low Hold
Min
80
40
40
15
15
35
20
15
2
30
40
30
Typ
Max
12.5
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK
CS
SDI
t
6
t
4
t
3
t
2
t
7
t
5
t
1
t
10
t
8
t
9
A3*
A2
t
12
t
11
A1
A0
D11
D10
D0
RESET
*ADDRESS BIT A3 MUST BE LOGIC LOW
0
Figure 2. Timing Diagram
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