RO
參數資料
型號: ADN4693EBRZ
廠商: Analog Devices Inc
文件頁數: 18/20頁
文件大?。?/td> 0K
描述: IC M-LVDS TRANSCEIVER
標準包裝: 56
系列: *
Data Sheet
ADN4691E/ADN4693E/ADN4696E/ADN4697E
Rev. A | Page 7 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
RO 1
RE 2
DE 3
DI 4
VCC
8
B
7
A
6
GND
5
ADN4691E/
ADN4696E
TOP VIEW
(Not to Scale)
10355-
003
Figure 3. ADN4691E/ADN4696E Pin Configuration
NC 1
2
3
4
VCC
14
13
12
11
5
10
GND 6
Y
9
GND 7
NC
8
NC = NO CONNECT
ADN4693E/
ADN4697E
TOP VIEW
(Not to Scale)
RO
RE
DE
DI
VCC
A
B
Z
1035
5-
004
Figure 4. ADN4693E/ADN4697E Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Pin No.
Mnemonic
Description
1
2
RO
Receiver Output. Type 1 receiver (ADN4691E/ADN4693E), when enabled:
If A B ≥ 50 mV, then RO = logic high. If A B ≤ 50 mV, then RO = logic low.
Type 2 receiver (ADN4696E/ADN4697E), when enabled:
If A B ≥ 150 mV, then RO = logic high. If A B ≤ 50 mV, then RO = logic low.
Receiver output is undefined outside these conditions.
2
3
RE
Receiver Output Enable. A logic low on this pin enables the receiver output, RO.
A logic high on this pin places RO in a high impedance state.
3
4
DE
Driver Output Enable. A logic high on this pin enables the driver differential outputs.
A logic low on this pin places the driver differential outputs in a high impedance state.
4
5
DI
Driver Input. Half-duplex (ADN4691E/ADN4696E), when enabled:
A logic low on DI forces A low and B high, whereas a logic high on DI forces A high and B low.
Full-duplex (ADN4693E/ADN4697E), when enabled:
A logic low on DI forces Y low and Z high, whereas a logic high on DI forces Y high and Z low.
5
6, 7
GND
Ground.
N/A
9
Y
Noninverting Driver Output Y.
N/A
10
Z
Inverting Driver Output Z.
6
N/A
A
Noninverting Receiver Input A and Noninverting Driver Output A.
N/A
12
A
Noninverting Receiver Input A.
7
N/A
B
Inverting Receiver Input B and Inverting Driver Output B.
N/A
11
B
Inverting Receiver Input B.
8
13, 14
VCC
Power Supply (3.3 V ± 0.3 V).
N/A
1, 8
NC
No Connect. Do not connect to these pins.
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