參數(shù)資料
型號： ADN4691EBRZ
廠商： Analog Devices Inc
文件頁數(shù)： 16/20頁
文件大小： 0K
描述： IC M-LVDS TRANSCEIVER
標準包裝： 98
系列： *
Data Sheet
ADN4691E/ADN4693E/ADN4696E/ADN4697E
Rev. A | Page 5 of 20
Table 4. Test Voltages for Type 2 Receiver
Applied Voltages
Input Voltage, Differential
Input Voltage, Common Mode
Receiver Output
VA (V)
VB (V)
VID (V)
VIC (V)
RO (V)
+2.4
0
+2.4
+1.2
H
0
+2.4
2.4
+1.2
L
+3.8
+3.65
+0.15
+3.725
H
+3.8
+3.75
+0.05
+3.775
L
1.25
1.4
+0.15
1.325
H
1.35
1.4
+0.05
1.375
L
TIMING SPECIFICATIONS
VCC = 3.0 V to 3.6 V; TA = TMIN to TMAX, unless otherwise noted.1
Table 5.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
DRIVER
Maximum Data Rate
200
Mbps
Propagation Delay
tPLH, tPHL
1
1.5
2.4
ns
Differential Output Rise/Fall Time
tR, tF
1
1.6
ns
Pulse Skew |tPHL – tPLH|
tSK
0
100
ps
Part-to-Part Skew2
tSK(PP)
1
ns
Period Jitter, RMS (1 Standard Deviation)3
tJ(PER)
2
3
ps
100 MHz clock input4 (see Figure 26)
Peak-to-Peak Jitter3, 5
tJ(PP)
30
130
ps
200 Mbps 215 1 PRBS input6 (see Figure 29)
Disable Time from High Level
tPHZ
7
ns
Disable Time from Low Level
tPLZ
7
ns
Enable Time to High Level
tPZH
7
ns
Enable Time to Low Level
tPZL
7
ns
RECEIVER
Propagation Delay
tRPLH, tRPHL
2
4
6
ns
CL = 15 pF (see Figure 30, Figure 33)
Rise/Fall Time
tR, tF
1
2.3
ns
CL = 15 pF (see Figure 30, Figure 33)
Pulse Skew |tRPHL – tRPLH|
tSK
CL = 15 pF (see Figure 30, Figure 33)
Type 1 Receiver (ADN4691E,
100
300
ps
Type 2 Receiver (ADN4696E,
300
500
ps
Part-to-Part Skew2
tSK(PP)
1
ns
CL = 15 pF (see Figure 30, Figure 33)
Period Jitter, RMS (1 Standard Deviation)3
tJ(PER)
4
7
ps
100 MHz clock input7 (see Figure 32)
Peak-to-Peak Jitter3, 5
tJ(PP)
200 Mbps 215 1 PRBS input8 (see Figure 35)
Type 1 Receiver (ADN4691E,
tJ(PP)
300
700
ps
Type 2 Receiver (ADN4696E,
450
800
ps
Disable Time from High Level
tRPHZ
10
ns
Disable Time from Low Level
tRPLZ
10
ns
Enable Time to High Level
tRPZH
15
ns
Enable Time to Low Level
tRPZL
15
ns
1 All typical values are given for VCC = 3.3 V and TA = 25°C.
2 tSK(PP) is defined as the difference between the propagation delays of two devices between any specified terminals. This specification applies to devices at the same VCC
and temperature, and with identical packages and test circuits.
3 Jitter parameters are guaranteed by design and characterization. Values do not include stimulus jitter.
4 tR = tF = 0.5 ns (10% to 90%), measured over 30,000 samples.
5 Peak-to-peak jitter specifications include jitter due to pulse skew (tSK).
6 tR = tF = 0.5 ns (10% to 90%), measured over 100,000 samples.
7 |VID| = 400 mV (ADN4696E, ADN4697E), Vic = 1.1 V, tR = tF = 0.5 ns (10% to 90%), measured over 30,000 samples.
8 |VID| = 400 mV (ADN4696E, ADN4697E), Vic = 1.1 V, tR = tF = 0.5 ns (10% to 90%), measured over 100,000 samples.
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ADN4691EBRZ-RL7 功能描述:IC TXRX MLVDS 200MBPS 8SOIC RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:* 標準包裝:121 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):1/1 規(guī)程:RS422，RS485 電源電壓:3 V ~ 3.6 V 安裝類型:表面貼裝 封裝/外殼:10-WFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:10-DFN（3x3） 包裝:管件
ADN4692E 制造商:AD 制造商全稱:Analog Devices 功能描述:3.3 V, 100 Mbps, Half- and Full-Duplex
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