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參數(shù)資料
| 型號： | ADN4668ARZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/12頁 |
| 文件大小： | 0K |
| 描述： | IC RCVR LVDS DIFF 4CH 16SOIC |
| 標準包裝： | 1,000 |
| 類型： | 線路接收器 |
| 驅(qū)動器/接收器數(shù)： | 0/4 |
| 規(guī)程： | LVDS |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
ADN4668
Rev. A | Page 7 of 12
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
RIN1+
RIN2+
RIN2–
RIN4+
RIN3+
RIN3–
RIN1–
RIN4–
16
15
14
13
12
11
10
9
ROUT1
ROUT2
VCC
ROUT4
EN
ROUT3
GND
EN
ADN4668
TOP VIEW
(Not to Scale)
07
23
7-
00
6
Figure 6. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
RIN1
Receiver Channel 1 Inverting Input. When this input is more negative than RIN1+, ROUT1 is high. When this input is
more positive than RIN1+, ROUT1 is low.
2
RIN1+
Receiver Channel 1 Noninverting Input. When this input is more positive than RIN1, ROUT1 is high. When this input
is more negative than RIN1, ROUT1 is low.
3
RIN2+
Receiver Channel 2 Noninverting Input. When this input is more positive than RIN2, ROUT2 is high. When this input
is more negative than RIN2, ROUT2 is low.
4
RIN2
Receiver Channel 2 Inverting Input. When this input is more negative than RIN2+, ROUT2 is high. When this input is
more positive than RIN2+, ROUT2 is low.
5
RIN3
Receiver Channel 3 Inverting Input. When this input is more negative than RIN3+, ROUT3 is high. When this input is
more positive than RIN3+, ROUT3 is low.
6
RIN3+
Receiver Channel 3 Noninverting Input. When this input is more positive than RIN3, ROUT3 is high. When this input
is more negative than RIN3, ROUT3 is low.
7
RIN4+
Receiver Channel 4 Noninverting Input. When this input is more positive than RIN4, ROUT4 is high. When this input
is more negative than RIN4, ROUT4 is low.
8
RIN4
Receiver Channel 4 Inverting Input. When this input is more negative than RIN4+, ROUT4 is high. When this input is
more positive than RIN4+, ROUT4 is low.
9
EN
Active-Low Enable and Power-Down Input with Pull-Down (3 V TTL/CMOS). When EN is held high, EN enables the
receiver outputs when EN is low or open circuit and puts the receiver outputs into a high impedance state and
powers down the device when EN is high.
10
ROUT4
Receiver Channel 4 Output (3 V TTL/CMOS). If the differential input voltage between RIN4+ and RIN4 is positive, this
output is high. If the differential input voltage is negative, this output is low.
11
ROUT3
Receiver Channel 3 Output (3 V TTL/CMOS). If the differential input voltage between RIN3+ and RIN3 is positive, this
output is high. If the differential input voltage is negative, this output is low.
12
GND
Ground Reference Point for All Circuitry on the Part.
13
VCC
Power Supply Input. These parts can be operated from 3.0 V to 3.6 V.
14
ROUT2
Receiver Channel 2 Output (3 V TTL/CMOS). If the differential input voltage between RIN2+ and RIN2 is positive, this
output is high. If the differential input voltage is negative, this output is low.
15
ROUT1
Receiver Channel 1 Output (3 V TTL/CMOS). If the differential input voltage between RIN1+ and RIN1 is positive, this
output is high. If the differential input voltage is negative, this output is low.
16
EN
Active-High Enable and Power-Down Input (3 V TTL/CMOS). When EN is held low or open circuit, EN enables the
receiver outputs when EN is high and puts the receiver outputs into a high impedance state and powers down
the device when EN is low.
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