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參數(shù)資料
| 型號： | ADN4667WARZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DRVR DIFF LVDS QUAD 16SOIC |
| 標準包裝： | 1,000 |
| 系列： | * |
ADN4667
Data Sheet
Rev. B | Page 4 of 16
AC CHARACTERISTICS
VCC = 3.0 V to 3.6 V; RL = 100 ; CL1 = 15 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. All typical values are given
for VCC = +3.3 V, TA = +25°C.
Table 2.
Min
Typ
Max
Unit
Differential Propagation Delay, High to Low, t
PHLD
0.5
0.9
1.7
ns
Differential Propagation Delay, Low to High, t
PLHD
0.5
1.2
1.7
ns
Differential Pulse Skew |t
PHLD tPLHD|, tSKD1
0
0.3
0.4
ns
Channel-to-Channel Skew, t
SKD2
0
0.4
0.5
ns
Differential Part-to-Part Skew, t
SKD3
0
1.0
ns
Differential Part-to-Part Skew, t
SKD4
0
1.2
ns
Rise Time, t
r
0.5
1.5
ns
Fall Time, t
f
0.5
1.5
ns
Disable Time High to Inactive, t
PHZ
2
5
ns
Disable Time Low to Inactive, t
PLZ
2
5
ns
Enable Time Inactive to High, t
PZH
3
7
ns
Enable Time Inactive to Low, t
PZL
3
7
ns
Maximum Operating Frequency, f
MAX
200
250
MHz
1 C
L includes probe and jig capacitance.
2 AC parameters are guaranteed by design and characterization.
3 Generator waveform for all tests unless otherwise specified: f = 50 MHz, Z
O = 50 Ω, tr ≤ 1 ns, and tf ≤ 1 ns.
4 All input voltages are for one channel unless otherwise specified. Other inputs are set to GND.
5 t
SKD1 = |tPHLD tPLHD| is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the
same channel.
6 t
SKD2 is the differential channel-to-channel skew of any event on the same device.
7 t
SKD3, differential part-to-part skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification
applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
8 t
SKD4, part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended operating
temperatures and voltage ranges, and across process distribution. tSKD4 is defined as |maximum minimum| differential propagation delay.
9 f
MAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% to 55%, VOD > 250 mV, all channels switching.
Test Circuits and Timing Diagrams
Figure 2. Test Circuit for Driver VOD and VOS
Figure 3. Test Circuit for Driver Propagation Delay and Transition Time
07032-
002
RL/2
DIN
DOUT+
DOUT–
VCC
VOS
VOD
DRIVER IS ENABLED
V
07032-
003
CL
DIN
DOUT+
DOUT–
DRIVER IS
ENABLED
NOTES
1. CL INCLUDES LOAD AND TEST JIG CAPACITANCE.
SIGNAL
GENERATOR
VCC
50
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