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參數(shù)資料
| 型號： | ADN4665ARZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DRIVER DIFF LVDS QUAD 16SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 線路驅(qū)動器，發(fā)射器 |
| 驅(qū)動器/接收器數(shù)： | 4/0 |
| 規(guī)程： | LVDS |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
ADN4665
Rev. 0 | Page 4 of 12
TIMING CHARACTERISTICS
VCC = 3.0 V to 3.6 V, RL = 100 Ω, CL1 = 15 pF to GND, all specifications TMIN to TMAX, unless otherwise noted. All typical values are given
for VCC = 3.3 V, TA = 25°C.
Table 2.
Parameter2
Symbol
Min
Typ
Max
Unit
AC CHARACTERISTICS
Differential Propagation Delay, High to Low
tPHLD
0.8
1.18
2.0
ns
Differential Propagation Delay, Low to High
tPLHD
0.8
1.25
2.0
ns
Differential Pulse Skew |tPHLD tPLHD|
tSKD15
0
0.07
0.4
ns
Channel-to-Channel Skew
tSKD26
0
0.1
0.5
ns
Differential Part-to-Part Skew
tSKD37
0
1.0
ns
Differential Part-to-Part Skew
tSKD48
0
1.2
ns
Rise Time
tTLH
0.38
1.5
ns
Fall Time
tTHL
0.4
1.5
ns
Disable Time High to Inactive
tPHZ
5
ns
Disable Time Low to Inactive
tPLZ
5
ns
Enable Time Inactive to High
tPZH
7
ns
Enable Time Inactive to Low
tPZL
7
ns
Maximum Operating Frequency
fMAX9
200
250
MHz
RL/2
DINx
DOUTx+
DOUTx–
VCC
VOS
VOD
NOTES
1. DRIVER IS ENABLED.
1 CL includes probe and jig capacitance.
2 AC parameters are guaranteed by design and characterization.
3 Generator waveform for all tests, unless otherwise specified: f = 50 MHz, ZO = 50 Ω, tr ≤ 1 ns, and tf ≤ 1 ns.
4 All input voltages are for one channel, unless otherwise specified. Other inputs are set to GND.
5 tSKD1 = |tPHLD tPLHD| is the magnitude difference in differential propagation delay time between the positive-going edge and the negative-going edge of the
same channel.
6 tSKD2 is the differential channel-to-channel skew of any event on the same device.
7 tSKD3, differential part-to-part skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification
applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
8 tSKD4, part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over the recommended operating
temperature and voltage ranges, and across process distribution. tSKD4 is defined as |maximum minimum| differential propagation delay.
9 fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% to 55%, VOD > 250 mV, all channels switching.
Test Circuits and Timing Diagrams
V
08
5-
0
02
Figure 2. Test Circuit for Driver VOD and VOS
CL
DINx
DOUTx+
DOUTx–
DRIVER IS
ENABLED
NOTES
1. CL INCLUDES PROBE AND JIG CAPACITANCE.
SIGNAL
GENERATOR
VCC
50
0
80
85
-0
03
Figure 3. Test Circuit for Driver Propagation Delay and Transition Time
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