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參數(shù)資料
| 型號(hào)： | ADN4663BRZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大小： | 0K |
| 描述： | IC DRIVER DIFF LVDS 2CH 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 98 |
| 類(lèi)型： | 驅(qū)動(dòng)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 2/0 |
| 規(guī)程： | LVDS |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁(yè)面： | 766 (CN2011-ZH PDF) |
ADN4663
Rev. 0 | Page 4 of 12
AC CHARACTERISTICS
VCC = 3.0 V to 3.6 V; RL = 100 Ω; CL1 = 15 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter2
Symbol
Min
Typ
Max
Unit
Conditions/Comments3, 4
Differential Propagation Delay High to Low
tPHLD
0.3
0.8
1.5
ns
Differential Propagation Delay Low to High
tPLHD
0.3
1.1
1.5
ns
tSKD1
0
0.3
0.7
ns
Channel-to-Channel Skew6
tSKD2
0
0.4
0.8
ns
Differential Part-to-Part Skew7
tSKD3
0
1.0
ns
Differential Part-to-Part Skew8
tSKD4
0
1.2
ns
Rise Time
tTLH
0.2
0.5
1.0
ns
Fall Time
tTHL
0.2
0.5
1.0
ns
Maximum Operating Frequency9
fMAX
350
MHz
See Figure 3
1 CL includes probe and jig capacitance.
2 AC parameters are guaranteed by design and characterization.
3 Generator waveform for all tests, unless otherwise specified: f = 50 MHz, ZO = 50 Ω, tTLH ≤ 1 ns, and tTHL ≤ 1 ns.
4 All input voltages are for one channel, unless otherwise specified. Other inputs are set to GND.
5 tSKD1 = |tPHLD tPLHD| is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the
same channel.
6 tSKD2 is the differential channel-to-channel skew of any event on the same device.
7 tSKD3, differential part-to-part skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification
applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
8 tSKD4, differential part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended
operating temperatures and voltage ranges, and across process distribution. tSKD4 is defined as |maximum minimum| differential propagation delay.
9 fMAX generator input conditions: tTLH = tTHL < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% to 55%, VOD > 250 mV, all channels
switching.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADN4663BRZ | 制造商:Analog Devices 功能描述:Transceiver IC |
| ADN4663BRZ1 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Dual, 3 V, CMOS, LVDS High Speed Differential Driver |
| ADN4663BRZ-REEL7 | 功能描述:IC DRIVER DIFF LVDS 2CH 8SOIC RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:121 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):1/1 規(guī)程:RS422，RS485 電源電壓:3 V ~ 3.6 V 安裝類(lèi)型:表面貼裝 封裝/外殼:10-WFDFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:10-DFN（3x3） 包裝:管件 |
| ADN4663BRZ-REEL71 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Dual, 3 V, CMOS, LVDS High Speed Differential Driver |
| ADN4664 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:LVDS and M-LVDS Circuit Implementation Guide |
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