參數(shù)資料
型號(hào)： ADN4605-EVALZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 32/56頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADN4605
標(biāo)準(zhǔn)包裝： 1
系列： *
其它名稱： Q6984339
ADN4605
Data Sheet
Rev. A | Page 38 of 56
PARALLEL CONTROL INTERFACE
The parallel control interface of the ADN4605 consists of
nineteen wires: ADDR[7:0], DATA[7:0], WE, RE, and CS. To
access the parallel control interface, the SER/PAR line must
be held at logic low. The CS line is used to select a device when
one or more devices share the same address and data lines. The
CS line must be held at logic low to enable write/read capability
to the device when in parallel control mode.
ADDRESS INPUTS: ADDR[7:0]
The binary coded address applied to the address lines
determines which device registers are being programmed or
read back.
DATA INPUTS/OUTPUTS: DATA[7:0]
In write mode, the binary encoded data applied to the data lines
(DATA[7:0]) determine the configuration setting of the register
specified by the address lines (ADDR[7:0]).
In read mode, data lines (DATA[7:0]) are low impedance
outputs indicating the data byte stored in the register specified
by the address lines (ADDR[7:0]). Note that some registers are
write only and may not be read from (see Table 19) The read-
back drivers are designed to drive high impedances only
(>1 k).
WRITE OPERATION
For first rank write enable, forcing this pin to logic low allows
the data on the DATA[7:0] lines to be stored in the first rank
latch for the register specified by the address lines (ADDR[7:0]).
The data is latched during the high-to-low transition of the
write enable pulse. The WE line must be returned to a logic
high state after the write cycle to avoid overwriting the first
rank data.
READ OPERATION
For second rank read enable, forcing this line to a logic low state
enables the output drivers on the bidirectional data lines
(DATA[7:0]), placing the logic in readback mode of operation.
The register selected to read from is determined by the binary
encoded data configured on the address lines (ADDR[7:0]).
When the read enable line is at a logic low, the data stored in
the specified register will be latched onto the data lines
(DATA[7:0]). The RE line is higher priority than the WE line;
therefore, first rank programming is not possible while in
readback mode. Note that some registers are defined as write
only and are not accessible in readback mode (see Table 19).
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