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| 型號： | ADN2891ACPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP LIM 16LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 放大器類型： | 限制 |
| 電路數(shù)： | 1 |
| 輸出類型： | 差分 |
| 電壓 - 輸入偏移： | 100µV |
| 電流 - 電源： | 45mA |
| 電壓 - 電源，單路/雙路(±)： | 2.9 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 95°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 16-LFCSP-VQ |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 788 (CN2011-ZH PDF) |
| 其它名稱： | ADN2891ACPZ-RL7DKR |
ADN2891
Rev. A | Page 10 of 16
THEORY OF OPERATION
LIMITING AMPLIFIER
Input Buffer
The ADN2891 limiting amplifier provides differential inputs
(PIN/NIN), each having single-ended, on-chip, 50 Ω termina-
tion. The amplifier can accept either dc-coupled or ac-coupled
signals; however, an ac-coupled signal is recommended. Using a
dc-coupled signal, the amplifier needs a correct input common-
mode voltage and enough headroom to handle the dynamic
input signal strength. Additionally, TIA output offset drifts may
degrade receiver performance.
The ADN2891 limiting amplifier is a high gain device. It is
susceptible to dc offsets in the signal path. The pulse width
distortion presented in the NRZ data or a distortion generated
by the TIA may appear as dc offset or a corrupted signal to the
ADN2891 inputs. An internal offset correction loop can
compensate for certain levels of offset. To compensate for more
offset, an external capacitor connected between the CAZ1 and
CAZ2 pins maybe necessary. For GbE and FC applications, no
external capacitor is necessary; however, for SONET appli-
cations, a 0.01 μF capacitor helps the input signal offset
compensation and provides a 3 dB cutoff frequency at 1 kHz.
CML Output Buffer
The ADN2891 provides differential CML outputs, OUTP and
OUTN. Each output has an internal 50 Ω termination to VCC.
LOSS OF SIGNAL (LOS) DETECTOR
The on-chip LOS circuit drives LOS to logic high when the
input signal level falls below a user-programmable threshold.
The threshold level can be set to anywhere from 3.5 mV p-p to
35 mV p-p, typical, and is set by a resistor connected between
LOS threshold vs. THRADJ. The ADN2891 LOS circuit has an
electrical hysteresis greater than 2.5 dB to prevent chatter at the
LOS signal. The LOS output is an open-collector output that
must be pulled up externally with a 4.7 kΩ to 10 kΩ resistor.
RECEIVED SIGNAL STRENGTH INDICATOR (RSSI)
The ADN2891 has an on-chip, RSSI circuit. By monitoring the
current supplied to the photodiode, the RSSI circuit provides an
accurate, average power measurement. The output of the RSSI is
a current that is directly proportional to the average amount of
PIN photodiode current. Placing a resistor between the
RSSI_OUT pin and GND converts the current to a GND
referenced voltage. This function eliminates the need for
external RSSI circuitry for SFF-8472-compliant optical
receivers. For more information, see Figure 14 to Figure 18.
SQUELCH MODE
Driving the SQUELCH input to logic high disables the limiting
amplifier outputs. Using LOS output to drive the SQUELCH
input, the limiting amplifier outputs stop toggling anytime a
signal input level to the limiting amplifier drops below the
programmed LOS threshold.
The SQUELCH pin has a 100 kΩ, internal, pull-down resistor.
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