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參數(shù)資料
| 型號(hào)： | ADN2849SURF |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 其它接口 |
| 英文描述： | 10.7 Gbps Electro-Absorption Modulator Driver |
| 中文描述： | SPECIALTY INTERFACE CIRCUIT, UUC27 |
| 封裝： | 2.05 X 2.05 MM, DIE-27 |
| 文件頁(yè)數(shù)： | 16/17頁(yè) |
| 文件大?。?/td> | 1425K |
| 代理商： | ADN2849SURF |
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ADN2849
DESIGN EXAMPLE
This section describes a design example that covers the
followings:
Rev. Pr. G | Page 16 of 17
Headroom calculation for the required bias offset and
modulation voltages
Required voltage range at the BIAS_SET and
MOD_SET pins to generate the required bias offset
and modulation voltages
This design example assumes a -5.2V supply voltage, 0.5V bias
offset voltage and 2V modulation voltage.
Headroom calculations
In order to operate properly, the bias offset and modulation
voltages must satisfy the following condition:
min
MODP
V
ffset
O
Bias
Modulation
V
VEE
V
≤
+
Assuming that V
MODPmin
=1.7V (see table1), the above condition
became:
V
5
7
2
V
5
=
≤
BIAS_SET voltage range
The voltage range at the BIAS_SET pin to generate 0.5V bias
offset voltage at the MODP pin can be calculated using the
BIAS_SET voltage to bias offset voltage gain specification from
table1 using the formulae:
min
OFFSET
K
BIAS
max
SET
_
BIAS
max
OFFSET
BIAS
K
min
SET
_
BIAS
V
V
V
V
=
=
Where K
min
and K
max
are the minimum and maximum values of
the BIAS_SET voltage to offset bias voltage gain from table1.
Substituting the values the BIAS_SET voltage range is 0.45V to
0.55V.
MOD_SET voltage range
The voltage range at the MOD_SET pin to generate 2V bias
offset voltage at the MODP pin can be calculated using the
MOD_SET voltage to bias offset voltage gain specification from
table1 using the formulae:
min
MODULATION
K
max
SET
_
MOD
max
MODULATION
K
min
SET
_
MOD
V
V
V
V
=
=
Where K
min
and K
max
are the minimum and maximum values of
the MOD_SET voltage to offset bias voltage gain from table1.
Substituting the values the MOD_SET voltage range is 1.05V to
1.33V.
Preliminary Technical Data
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